[PATCH v3 0/4] Improve Mips target

[PATCH v3 0/4] Improve Mips target

[Aleksandar Rakic]

This patch series adds support for emulation of CRC32 instructions for
the Mips target in QEMU, skips NaN mode check for soft-float, adds a CLI
flag for enabling an MSA feature, and enables the MSA for
MIPS64R2-generic.

There aren't tests for these improvements.

The patch 1/8 "Add CP0 MemoryMapID register implementation" from v2 has
been dropped from v3 since it has been accepted and integrated into the
master branch.

The patch 3/8 "GTM19-448: Fix script to work without realpath" from v2
will be sent separately as it is a fix to a general bug and is intended
for other maintainers.

The patch 5/8 "Add micromips to P5600" from v2 has been dropped from v3
since the latest document for P5600 with eventually updated field
CP0_Config3_ISA that would support microMIPS hasn't been found.

The patch 6/8 "Revert use of clock_gettime for benchmarking" from v2 has
been dropped from v3 because it seems that clock_gettime and
CLOCK_MONOTONIC exist in MinGW headers and that QEMU builds with MinGW.

The patch 7/8 "target/mips: Enable MSA ASE for mips32r6-generic" from v2
has been dropped from v3 since it has been accepted and integrated into
the master branch.

When it comes to the patch 8/8 "target/mips: Enable MSA ASE for
mips64R2-generic" from v2, the cpu Loongson-3A4000 supports both
mips64r2 and the MSA, so I'm not sure whether to drop this patch.

Regarding the DSPRAM for I6500, I heard that the IP for the DSPRAM for
mips64r6 hasn't been published, but in the document "MIPS64® I6500
Multiprocessing System Programmer’s Guide" the DSPRAM is elaborated, so
I don't know whether to add support for the DSPRAM.

Most of the following patches are cherry-picked from the branch
mips_rel/4_1_0/master on the MIPS' repository:
https://github.com/MIPS/gnutools-qemu/
Further details on individual changes are included in the respective
patches. An instance of a pipeline of QEMU CI jobs run with input
variable QEMU_CI=1 for this patch series is available here:
https://gitlab.com/rakicaleksandar1999/qemu/-/pipelines/1533819034
and for the master branch is available here:
https://gitlab.com/rakicaleksandar1999/qemu/-/pipelines/1533465414

We are open for a discussion.

[PATCH v3 0/4] Improve Mips target

[Aleksandar Rakic]

Aleksandar Rakic (4):
  Add support for emulation of CRC32 instructions
  Skip NaN mode check for soft-float
  target/mips: Enable MSA ASE using a CLI flag
  target/mips: Enable MSA ASE for mips64R2-generic

 linux-user/mips/cpu_loop.c       |  6 ++++--
 target/mips/cpu-defs.c.inc       |  4 +++-
 target/mips/cpu.c                | 16 ++++++++++++++++
 target/mips/cpu.h                |  1 +
 target/mips/helper.h             |  2 ++
 target/mips/internal.h           |  2 +-
 target/mips/meson.build          |  1 +
 target/mips/tcg/op_helper.c      | 26 ++++++++++++++++++++++++++
 target/mips/tcg/rel6.decode      |  5 +++++
 target/mips/tcg/rel6_translate.c | 14 ++++++++++++++
 target/mips/tcg/translate.c      | 25 +++++++++++++++++++++++++
 target/mips/tcg/translate.h      |  3 +++
 12 files changed, 101 insertions(+), 4 deletions(-)

-- 
2.34.1

[PATCH v3 1/4] Add support for emulation of CRC32 instructions

[Aleksandar Rakic]

Add emulation of MIPS' CRC32 (Cyclic Redundancy Check) instructions.
Reuse zlib crc32() and Linux crc32c().

Cherry-picked 4cc974938aee1588f852590509004e340c072940
from https://github.com/MIPS/gnutools-qemu

Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Aleksandar Rakic <aleksandar.rakic@htecgroup.com>
Reviewed-by: Aleksandar Rikalo <arikalo@gmail.com>
---
 target/mips/helper.h             |  2 ++
 target/mips/meson.build          |  1 +
 target/mips/tcg/op_helper.c      | 26 ++++++++++++++++++++++++++
 target/mips/tcg/rel6.decode      |  5 +++++
 target/mips/tcg/rel6_translate.c | 14 ++++++++++++++
 target/mips/tcg/translate.c      | 25 +++++++++++++++++++++++++
 target/mips/tcg/translate.h      |  3 +++
 7 files changed, 76 insertions(+)

diff --git a/target/mips/helper.h b/target/mips/helper.h
index 0f8462febb..752748d5e6 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -21,6 +21,8 @@ DEF_HELPER_FLAGS_1(bitswap, TCG_CALL_NO_RWG_SE, tl, tl)
 DEF_HELPER_FLAGS_1(dbitswap, TCG_CALL_NO_RWG_SE, tl, tl)
 #endif
 
+DEF_HELPER_3(crc32, tl, tl, tl, i32)
+DEF_HELPER_3(crc32c, tl, tl, tl, i32)
 DEF_HELPER_FLAGS_4(rotx, TCG_CALL_NO_RWG_SE, tl, tl, i32, i32, i32)
 
 /* microMIPS functions */
diff --git a/target/mips/meson.build b/target/mips/meson.build
index a26d1e1f79..d2d686fc0c 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -7,6 +7,7 @@ mips_ss.add(files(
   'gdbstub.c',
   'msa.c',
 ))
+mips_ss.add(zlib)
 
 if have_system
   subdir('sysemu')
diff --git a/target/mips/tcg/op_helper.c b/target/mips/tcg/op_helper.c
index 65403f1a87..22600697f0 100644
--- a/target/mips/tcg/op_helper.c
+++ b/target/mips/tcg/op_helper.c
@@ -25,6 +25,8 @@
 #include "exec/exec-all.h"
 #include "exec/memop.h"
 #include "fpu_helper.h"
+#include "qemu/crc32c.h"
+#include <zlib.h>
 
 static inline target_ulong bitswap(target_ulong v)
 {
@@ -143,6 +145,30 @@ target_ulong helper_rotx(target_ulong rs, uint32_t shift, uint32_t shiftx,
     return (int64_t)(int32_t)(uint32_t)tmp5;
 }
 
+/* these crc32 functions are based on target/arm/helper-a64.c */
+target_ulong helper_crc32(target_ulong val, target_ulong m, uint32_t sz)
+{
+    uint8_t buf[8];
+    target_ulong mask = ((sz * 8) == 64) ?
+                        (target_ulong) -1ULL :
+                        ((1ULL << (sz * 8)) - 1);
+
+    m &= mask;
+    stq_le_p(buf, m);
+    return (int32_t) (crc32(val ^ 0xffffffff, buf, sz) ^ 0xffffffff);
+}
+
+target_ulong helper_crc32c(target_ulong val, target_ulong m, uint32_t sz)
+{
+    uint8_t buf[8];
+    target_ulong mask = ((sz * 8) == 64) ?
+                        (target_ulong) -1ULL :
+                        ((1ULL << (sz * 8)) - 1);
+    m &= mask;
+    stq_le_p(buf, m);
+    return (int32_t) (crc32c(val, buf, sz) ^ 0xffffffff);
+}
+
 void helper_fork(target_ulong arg1, target_ulong arg2)
 {
     /*
diff --git a/target/mips/tcg/rel6.decode b/target/mips/tcg/rel6.decode
index d6989cf56e..5074338aa5 100644
--- a/target/mips/tcg/rel6.decode
+++ b/target/mips/tcg/rel6.decode
@@ -16,11 +16,16 @@
 
 &r                  rs rt rd sa
 
+&special3_crc       rs rt c sz
+
 @lsa                ...... rs:5 rt:5 rd:5 ... sa:2 ......   &r
+@crc32              ...... rs:5 rt:5 ..... c:3 sz:2 ......   &special3_crc
 
 LSA                 000000 ..... ..... ..... 000 .. 000101  @lsa
 DLSA                000000 ..... ..... ..... 000 .. 010101  @lsa
 
+CRC32               011111 ..... ..... 00000 ... .. 001111  @crc32
+
 REMOVED             010011 ----- ----- ----- ----- ------   # COP1X (COP3)
 
 REMOVED             011100 ----- ----- ----- ----- ------   # SPECIAL2
diff --git a/target/mips/tcg/rel6_translate.c b/target/mips/tcg/rel6_translate.c
index 59f237ba3b..423b323ba7 100644
--- a/target/mips/tcg/rel6_translate.c
+++ b/target/mips/tcg/rel6_translate.c
@@ -33,3 +33,17 @@ static bool trans_DLSA(DisasContext *ctx, arg_r *a)
     }
     return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa);
 }
+
+static bool trans_CRC32(DisasContext *ctx, arg_special3_crc *a)
+{
+    if (unlikely(!ctx->crcp) ||
+        unlikely((a->sz == 3) &&
+                 (!(ctx->hflags & MIPS_HFLAG_64))) ||
+        unlikely((a->c >= 2))) {
+        gen_reserved_instruction(ctx);
+        return true;
+    }
+    gen_crc32(ctx, a->rt, a->rs, a->rt,
+              a->sz, a->c);
+    return true;
+}
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index de7045874d..c97d1d37bd 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -13448,6 +13448,30 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
     }
 }
 
+void gen_crc32(DisasContext *ctx, int rd, int rs, int rt, int sz,
+                      int crc32c)
+{
+    TCGv t0;
+    TCGv t1;
+    TCGv_i32 tsz = tcg_constant_i32(1 << sz);
+    if (rd == 0) {
+        /* Treat as NOP. */
+        return;
+    }
+    t0 = tcg_temp_new();
+    t1 = tcg_temp_new();
+
+    gen_load_gpr(t0, rt);
+    gen_load_gpr(t1, rs);
+
+    if (crc32c) {
+        gen_helper_crc32c(cpu_gpr[rd], t0, t1, tsz);
+    } else {
+        gen_helper_crc32(cpu_gpr[rd], t0, t1, tsz);
+    }
+
+}
+
 static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
 {
     int rs, rt, rd, sa;
@@ -15094,6 +15118,7 @@ static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     ctx->abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1;
     ctx->mi = (env->CP0_Config5 >> CP0C5_MI) & 1;
     ctx->gi = (env->CP0_Config5 >> CP0C5_GI) & 3;
+    ctx->crcp = (env->CP0_Config5 >> CP0C5_CRCP) & 1;
     restore_cpu_state(env, ctx);
 #ifdef CONFIG_USER_ONLY
         ctx->mem_idx = MIPS_HFLAG_UM;
diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h
index 1bf153d183..cb27ae78ae 100644
--- a/target/mips/tcg/translate.h
+++ b/target/mips/tcg/translate.h
@@ -51,6 +51,7 @@ typedef struct DisasContext {
     bool abs2008;
     bool mi;
     int gi;
+    bool crcp;
 } DisasContext;
 
 #define DISAS_STOP       DISAS_TARGET_0
@@ -181,6 +182,8 @@ bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa);
 bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa);
 
 void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel);
+void gen_crc32(DisasContext *ctx, int rd, int rs, int rt, int sz,
+               int crc32c);
 
 extern TCGv cpu_gpr[32], cpu_PC;
 #if defined(TARGET_MIPS64)
-- 
2.34.1

Re: [PATCH v3 1/4] Add support for emulation of CRC32 instructions

[Aleksandar Rakic]

Hi,

A kind remind/ping on the patch. Before we send v3,
do you have any comments on this patch?

Kind regards,
Aleksandar Rakic

Re: [PATCH v3 1/4] Add support for emulation of CRC32 instructions

[Aleksandar Rakic]

Hi,

Could you please let us know if you have any comments
on the latest version of this patch?

Kind regards,
Aleksandar Rakic

Re: [PATCH v3 1/4] Add support for emulation of CRC32 instructions

[Philippe Mathieu-Daudé]

On 12/11/24 17:41, Aleksandar Rakic wrote:
> Add emulation of MIPS' CRC32 (Cyclic Redundancy Check) instructions.
> Reuse zlib crc32() and Linux crc32c().
> 
> Cherry-picked 4cc974938aee1588f852590509004e340c072940
> from https://github.com/MIPS/gnutools-qemu
> 
> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> Signed-off-by: Aleksandar Rakic <aleksandar.rakic@htecgroup.com>
> Reviewed-by: Aleksandar Rikalo <arikalo@gmail.com>
> ---
>   target/mips/helper.h             |  2 ++
>   target/mips/meson.build          |  1 +
>   target/mips/tcg/op_helper.c      | 26 ++++++++++++++++++++++++++
>   target/mips/tcg/rel6.decode      |  5 +++++
>   target/mips/tcg/rel6_translate.c | 14 ++++++++++++++
>   target/mips/tcg/translate.c      | 25 +++++++++++++++++++++++++
>   target/mips/tcg/translate.h      |  3 +++
>   7 files changed, 76 insertions(+)

Thanks Aleksandar, could you add a pair of tests in
tests/tcg/mips/user/isa/mips64r6/?

Re: [PATCH v3 1/4] Add support for emulation of CRC32 instructions

[Philippe Mathieu-Daudé]

On 12/11/24 17:41, Aleksandar Rakic wrote:
> Add emulation of MIPS' CRC32 (Cyclic Redundancy Check) instructions.
> Reuse zlib crc32() and Linux crc32c().
> 
> Cherry-picked 4cc974938aee1588f852590509004e340c072940
> from https://github.com/MIPS/gnutools-qemu
> 
> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> Signed-off-by: Aleksandar Rakic <aleksandar.rakic@htecgroup.com>
> Reviewed-by: Aleksandar Rikalo <arikalo@gmail.com>
> ---
>   target/mips/helper.h             |  2 ++
>   target/mips/meson.build          |  1 +
>   target/mips/tcg/op_helper.c      | 26 ++++++++++++++++++++++++++
>   target/mips/tcg/rel6.decode      |  5 +++++
>   target/mips/tcg/rel6_translate.c | 14 ++++++++++++++
>   target/mips/tcg/translate.c      | 25 +++++++++++++++++++++++++
>   target/mips/tcg/translate.h      |  3 +++
>   7 files changed, 76 insertions(+)


> diff --git a/target/mips/tcg/rel6.decode b/target/mips/tcg/rel6.decode
> index d6989cf56e..5074338aa5 100644
> --- a/target/mips/tcg/rel6.decode
> +++ b/target/mips/tcg/rel6.decode
> @@ -16,11 +16,16 @@
>   
>   &r                  rs rt rd sa
>   
> +&special3_crc       rs rt c sz
> +
>   @lsa                ...... rs:5 rt:5 rd:5 ... sa:2 ......   &r
> +@crc32              ...... rs:5 rt:5 ..... c:3 sz:2 ......   &special3_crc
>   
>   LSA                 000000 ..... ..... ..... 000 .. 000101  @lsa
>   DLSA                000000 ..... ..... ..... 000 .. 010101  @lsa
>   
> +CRC32               011111 ..... ..... 00000 ... .. 001111  @crc32

Interestingly the disassembly for that is in tree, hidden in commit
99029be1c28 ("target/mips: Add implementation of GINVT instruction")...

Re: [PATCH v3 1/4] Add support for emulation of CRC32 instructions

[Philippe Mathieu-Daudé]

On 22/1/25 08:27, Philippe Mathieu-Daudé wrote:
> On 12/11/24 17:41, Aleksandar Rakic wrote:
>> Add emulation of MIPS' CRC32 (Cyclic Redundancy Check) instructions.
>> Reuse zlib crc32() and Linux crc32c().
>>
>> Cherry-picked 4cc974938aee1588f852590509004e340c072940
>> from https://github.com/MIPS/gnutools-qemu
>>
>> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
>> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
>> Signed-off-by: Aleksandar Rakic <aleksandar.rakic@htecgroup.com>
>> Reviewed-by: Aleksandar Rikalo <arikalo@gmail.com>
>> ---
>>   target/mips/helper.h             |  2 ++
>>   target/mips/meson.build          |  1 +
>>   target/mips/tcg/op_helper.c      | 26 ++++++++++++++++++++++++++
>>   target/mips/tcg/rel6.decode      |  5 +++++
>>   target/mips/tcg/rel6_translate.c | 14 ++++++++++++++
>>   target/mips/tcg/translate.c      | 25 +++++++++++++++++++++++++
>>   target/mips/tcg/translate.h      |  3 +++
>>   7 files changed, 76 insertions(+)
> 
> 
>> diff --git a/target/mips/tcg/rel6.decode b/target/mips/tcg/rel6.decode
>> index d6989cf56e..5074338aa5 100644
>> --- a/target/mips/tcg/rel6.decode
>> +++ b/target/mips/tcg/rel6.decode
>> @@ -16,11 +16,16 @@
>>   &r                  rs rt rd sa
>> +&special3_crc       rs rt c sz
>> +
>>   @lsa                ...... rs:5 rt:5 rd:5 ... sa:2 ......   &r
>> +@crc32              ...... rs:5 rt:5 ..... c:3 sz:2 ......   
>> &special3_crc
>>   LSA                 000000 ..... ..... ..... 000 .. 000101  @lsa
>>   DLSA                000000 ..... ..... ..... 000 .. 010101  @lsa
>> +CRC32               011111 ..... ..... 00000 ... .. 001111  @crc32

Are these really available on MIPS64? (Looking at MD00087 Revision 6.05)

> Interestingly the disassembly for that is in tree, hidden in commit
> 99029be1c28 ("target/mips: Add implementation of GINVT instruction")...

[PATCH v3 2/4] Skip NaN mode check for soft-float

[Aleksandar Rakic]

Skip NaN mode check for soft-float since NaN mode is irrelevant if an ELF
binary's FPU mode is soft-float, i.e. it doesn't utilize a FPU.

Cherry-picked 63492a56485f6b755fccf7ad623f7a189bfc79b6
from https://github.com/MIPS/gnutools-qemu

Signed-off-by: Faraz Shahbazker <fshahbazker@wavecomp.com>
Signed-off-by: Aleksandar Rakic <aleksandar.rakic@htecgroup.com>
---
 linux-user/mips/cpu_loop.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c
index 462387a073..07c1ebe287 100644
--- a/linux-user/mips/cpu_loop.c
+++ b/linux-user/mips/cpu_loop.c
@@ -304,8 +304,10 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
     if (env->insn_flags & ISA_NANOMIPS32) {
         return;
     }
-    if (((info->elf_flags & EF_MIPS_NAN2008) != 0) !=
-        ((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) != 0)) {
+    if (info->fp_abi != MIPS_ABI_FP_SOFT
+        && ((info->elf_flags & EF_MIPS_NAN2008) != 0) !=
+           ((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) != 0))
+      {
         if ((env->active_fpu.fcr31_rw_bitmask &
               (1 << FCR31_NAN2008)) == 0) {
             fprintf(stderr, "ELF binary's NaN mode not supported by CPU\n");
-- 
2.34.1

Re: [PATCH v3 2/4] Skip NaN mode check for soft-float

[Aleksandar Rakic]

Hi,

A kind remind/ping on the patch. Before we send v3,
do you have any comments on this patch?

Kind regards,
Aleksandar Rakic

Re: [PATCH v3 2/4] Skip NaN mode check for soft-float

[Aleksandar Rakic]

Hi,

Could you please let us know if you have any comments
on the latest version of this patch?

Kind regards,
Aleksandar Rakic

[PATCH v3 3/4] target/mips: Enable MSA ASE using a CLI flag

[Aleksandar Rakic]

Enable MSA ASE using a CLI flag -cpu <cpu>,msa=on.

Signed-off-by: Aleksandar Rakic <aleksandar.rakic@htecgroup.com>
---
 target/mips/cpu.c      | 16 ++++++++++++++++
 target/mips/cpu.h      |  1 +
 target/mips/internal.h |  2 +-
 3 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index d0a43b6d5c..8e12d303de 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -494,8 +494,24 @@ static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
     mcc->parent_realize(dev, errp);
 }
 
+static bool mips_get_msa_on(Object *obj, Error **errp)
+{
+    MIPSCPU *cpu = MIPS_CPU(obj);
+    CPUMIPSState *env = &cpu->env;
+    return env->msa_on;
+}
+
+static void mips_set_msa_on(Object *obj, bool value, Error **errp)
+{
+    MIPSCPU *cpu = MIPS_CPU(obj);
+    CPUMIPSState *env = &cpu->env;
+    env->msa_on = value;
+}
+
 static void mips_cpu_initfn(Object *obj)
 {
+    object_property_add_bool(obj, "msa", mips_get_msa_on, mips_set_msa_on);
+    object_property_set_bool(obj, "msa", false, NULL);
     MIPSCPU *cpu = MIPS_CPU(obj);
     CPUMIPSState *env = &cpu->env;
     MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(obj);
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index f6877ece8b..3e636535c6 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1191,6 +1191,7 @@ typedef struct CPUArchState {
     QEMUTimer *timer; /* Internal timer */
     Clock *count_clock; /* CP0_Count clock */
     target_ulong exception_base; /* ExceptionBase input to the core */
+    bool msa_on; /* Enable MSA using a CLI flag -cpu ...,msa=on/off */
 } CPUMIPSState;
 
 /**
diff --git a/target/mips/internal.h b/target/mips/internal.h
index 91c786cff8..bbe2acffe2 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -399,7 +399,7 @@ static inline void compute_hflags(CPUMIPSState *env)
         }
     }
     if (ase_msa_available(env)) {
-        if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) {
+        if ((env->CP0_Config5 & (1 << CP0C5_MSAEn)) || (env->msa_on)) {
             env->hflags |= MIPS_HFLAG_MSA;
         }
     }
-- 
2.34.1

Re: [PATCH v3 3/4] target/mips: Enable MSA ASE using a CLI flag

[Aleksandar Rakic]

Hi,

A kind remind/ping on the patch. Before we send v3,
do you have any comments on this patch?

Kind regards,
Aleksandar Rakic

Re: [PATCH v3 3/4] target/mips: Enable MSA ASE using a CLI flag

[Aleksandar Rakic]

Hi,

Could you please let us know if you have any comments
on the latest version of this patch?

Kind regards,
Aleksandar Rakic

[PATCH v3 4/4] target/mips: Enable MSA ASE for mips64R2-generic

[Aleksandar Rakic]

Enable MSA ASE for mips64R2-generic CPU.

Cherry-picked 60f6ae8d3d685ba1ea5d301222fb72b67f39264f
from  https://github.com/MIPS/gnutools-qemu

Signed-off-by: Faraz Shahbazker <fshahbazker@wavecomp.com>
Signed-off-by: Aleksandar Rakic <aleksandar.rakic@htecgroup.com>
---
 target/mips/cpu-defs.c.inc | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
index 922fc39138..e77a327422 100644
--- a/target/mips/cpu-defs.c.inc
+++ b/target/mips/cpu-defs.c.inc
@@ -678,7 +678,9 @@ const mips_def_t mips_defs[] =
                        (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
                        (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
         .CP0_Config2 = MIPS_CONFIG2,
-        .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
+        .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA) |
+                       (1 << CP0C3_VInt) | (1 << CP0C3_MSAP),
+        .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn),
         .CP0_LLAddr_rw_bitmask = 0,
         .CP0_LLAddr_shift = 0,
         .SYNCI_Step = 32,
-- 
2.34.1

Re: [PATCH v3 4/4] target/mips: Enable MSA ASE for mips64R2-generic

[Philippe Mathieu-Daudé]

On 12/11/24 16:41, Aleksandar Rakic wrote:
> Enable MSA ASE for mips64R2-generic CPU.
> 
> Cherry-picked 60f6ae8d3d685ba1ea5d301222fb72b67f39264f
> from  https://github.com/MIPS/gnutools-qemu
> 
> Signed-off-by: Faraz Shahbazker <fshahbazker@wavecomp.com>
> Signed-off-by: Aleksandar Rakic <aleksandar.rakic@htecgroup.com>
> ---
>   target/mips/cpu-defs.c.inc | 4 +++-
>   1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
> index 922fc39138..e77a327422 100644
> --- a/target/mips/cpu-defs.c.inc
> +++ b/target/mips/cpu-defs.c.inc
> @@ -678,7 +678,9 @@ const mips_def_t mips_defs[] =
>                          (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
>                          (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
>           .CP0_Config2 = MIPS_CONFIG2,
> -        .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
> +        .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA) |
> +                       (1 << CP0C3_VInt) | (1 << CP0C3_MSAP),
> +        .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn),

See v2:
https://lore.kernel.org/qemu-devel/50dd60b2-f789-4828-9a7e-3becc6721964@linaro.org/

>           .CP0_LLAddr_rw_bitmask = 0,
>           .CP0_LLAddr_shift = 0,
>           .SYNCI_Step = 32,