From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: "Corvin Köhne" <corvin.koehne@gmail.com>, qemu-devel@nongnu.org
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
"Yannick Voßen" <y.vossen@beckhoff.com>,
qemu-block@nongnu.org, "Paolo Bonzini" <pbonzini@redhat.com>,
"Hanna Reitz" <hreitz@redhat.com>,
"Alistair Francis" <alistair@alistair23.me>,
qemu-arm@nongnu.org, "Corvin Köhne" <c.koehne@beckhoff.com>,
"Kevin Wolf" <kwolf@redhat.com>,
"Edgar E. Iglesias" <edgar.iglesias@gmail.com>
Subject: Re: [PATCH v4 01/15] hw/timer: Make frequency configurable
Date: Wed, 12 Nov 2025 12:24:20 +0100 [thread overview]
Message-ID: <9bc047f0-1122-4381-ab5a-01878a10297e@linaro.org> (raw)
In-Reply-To: <20251111102836.212535-2-corvin.koehne@gmail.com>
Hi Yannick, Corvin.
On 11/11/25 11:28, Corvin Köhne wrote:
> From: YannickV <Y.Vossen@beckhoff.com>
>
> The a9 global timer and arm mp timers rely on the PERIPHCLK as
> their clock source. The current implementation does not take
> that into account. That causes problems for applications assuming
> other frequencies than 1 GHz.
This change makes sense, but IMHO we should model the source as a
Clock object (see docs/devel/clocks.rst).
> We can now configure frequencies for the a9 global timer and
> arm mp timer. By allowing these values to be set according to
> the application's needs, we ensure that the timers behave
> consistently with the expected system configuration. The SoC
> configures the device correctly.
>
> Information can be found in the Zynq 7000 SoC Technical
> Reference Manual under Timers.
> https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM
>
> Signed-off-by: YannickV <Y.Vossen@beckhoff.com>
> ---
> hw/timer/a9gtimer.c | 9 ++++++---
> hw/timer/arm_mptimer.c | 15 +++++++++++----
> include/hw/timer/a9gtimer.h | 1 +
> include/hw/timer/arm_mptimer.h | 2 ++
> 4 files changed, 20 insertions(+), 7 deletions(-)
next prev parent reply other threads:[~2025-11-12 11:27 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-11 10:28 [PATCH v4 00/15] hw/arm: add Beckhoff CX7200 board Corvin Köhne
2025-11-11 10:28 ` [PATCH v4 01/15] hw/timer: Make frequency configurable Corvin Köhne
2025-11-12 11:24 ` Philippe Mathieu-Daudé [this message]
2025-11-11 10:28 ` [PATCH v4 02/15] hw/timer: Make PERIPHCLK divider configurable Corvin Köhne
2025-11-12 11:25 ` Philippe Mathieu-Daudé
2025-11-11 10:28 ` [PATCH v4 03/15] hw/dma/zynq-devcfg: Handle bitstream loading via DMA to 0xffffffff Corvin Köhne
2025-11-11 10:28 ` [PATCH v4 04/15] hw/arm/zynq-devcfg: Prevent unintended unlock during initialization Corvin Köhne
2025-11-12 11:27 ` Philippe Mathieu-Daudé
2025-11-11 10:28 ` [PATCH v4 05/15] hw/dma/zynq: Ensure PCFG_DONE bit remains set to indicate PL is in user mode Corvin Köhne
2025-11-11 10:28 ` [PATCH v4 06/15] hw/dma/zynq-devcfg: Simulate dummy PL reset Corvin Köhne
2025-11-11 10:28 ` [PATCH v4 07/15] hw/dma/zynq-devcfg: Indicate power-up status of PL Corvin Köhne
2025-11-11 10:28 ` [PATCH v4 08/15] hw/dma/zynq-devcfg: Fix register memory Corvin Köhne
2025-11-12 11:31 ` [PATCH-for-10.2 " Philippe Mathieu-Daudé
2025-11-11 10:28 ` [PATCH v4 09/15] hw/misc: Add dummy ZYNQ DDR controller Corvin Köhne
2025-11-11 10:28 ` [PATCH v4 10/15] hw/misc/zynq_slcr: Add logic for DCI configuration Corvin Köhne
2025-11-11 10:28 ` [PATCH v4 11/15] hw/misc: Add Beckhoff CCAT device Corvin Köhne
2025-11-12 11:36 ` Philippe Mathieu-Daudé
2025-11-11 10:28 ` [PATCH v4 12/15] hw/block/m25p80: Add HAS_SR_TB flag for is25lp016d Corvin Köhne
2025-11-11 10:28 ` [PATCH v4 13/15] hw/arm: Add new machine based on xilinx-zynq-a9 for Beckhoff CX7200 Corvin Köhne
2025-11-12 11:43 ` Philippe Mathieu-Daudé
2025-11-11 10:28 ` [PATCH v4 14/15] tests/functional: Add a Beckhoff CX7200 test Corvin Köhne
2025-11-12 11:44 ` Philippe Mathieu-Daudé
2025-11-11 10:28 ` [PATCH v4 15/15] docs/system/arm: Add support for Beckhoff CX7200 Corvin Köhne
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