* [PATCH v2 0/2] Supporting AST2600 HACE engine accumulative mode @ 2022-01-12 8:09 Troy Lee 2022-01-12 8:09 ` [PATCH v2 1/2] hw/misc: Supporting AST2600 HACE " Troy Lee 2022-01-12 8:09 ` [PATCH v2 2/2] tests/qtest: Add test for Aspeed " Troy Lee 0 siblings, 2 replies; 9+ messages in thread From: Troy Lee @ 2022-01-12 8:09 UTC (permalink / raw) To: qemu-devel; +Cc: leetroy, hailin.wu This patch series implements ast2600 hace engine with accumulative mode and unit test against to it. Changes in v2: - Coding style - Add accumulative mode description in comment - Add unit test cases Troy Lee (2): hw/misc: Supporting AST2600 HACE accumulative mode tests/qtest: Add test for Aspeed HACE accumulative mode hw/misc/aspeed_hace.c | 43 ++++++++-- include/hw/misc/aspeed_hace.h | 1 + tests/qtest/aspeed_hace-test.c | 145 +++++++++++++++++++++++++++++++++ 3 files changed, 181 insertions(+), 8 deletions(-) -- 2.25.1 ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 1/2] hw/misc: Supporting AST2600 HACE accumulative mode 2022-01-12 8:09 [PATCH v2 0/2] Supporting AST2600 HACE engine accumulative mode Troy Lee @ 2022-01-12 8:09 ` Troy Lee 2022-01-12 8:12 ` Troy Lee ` (2 more replies) 2022-01-12 8:09 ` [PATCH v2 2/2] tests/qtest: Add test for Aspeed " Troy Lee 1 sibling, 3 replies; 9+ messages in thread From: Troy Lee @ 2022-01-12 8:09 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, Andrew Jeffery, hailin.wu, leetroy, open list:ASPEED BMCs, Cédric Le Goater, Joel Stanley Accumulative mode will supply a initial state and append padding bit at the end of hash stream. However, the crypto library will padding those bit automatically, so ripped it off from iov array. The aspeed ast2600 acculumative mode is described in datasheet ast2600v10.pdf section 25.6.4: 1. Allocationg and initiating accumulative hash digest write buffer with initial state. * Since QEMU crypto/hash api doesn't provide the API to set initial state of hash library, and the initial state is already setted by crypto library (gcrypt/glib/...), so skip this step. 2. Calculating accumulative hash digest. (a) When receiving the last accumulative data, software need to add padding message at the end of the accumulative data. Padding message described in specific of MD5, SHA-1, SHA224, SHA256, SHA512, SHA512/224, SHA512/256. * Since the crypto library (gcrypt/glib) already pad the padding message internally. * This patch is to remove the padding message which fed byguest machine driver. Changes in v2: - Coding style - Add accumulative mode description in comment Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> --- hw/misc/aspeed_hace.c | 43 ++++++++++++++++++++++++++++------- include/hw/misc/aspeed_hace.h | 1 + 2 files changed, 36 insertions(+), 8 deletions(-) diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index 10f00e65f4..0710f44621 100644 --- a/hw/misc/aspeed_hace.c +++ b/hw/misc/aspeed_hace.c @@ -11,6 +11,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "qemu/error-report.h" +#include "qemu/bswap.h" #include "hw/misc/aspeed_hace.h" #include "qapi/error.h" #include "migration/vmstate.h" @@ -27,6 +28,7 @@ #define R_HASH_SRC (0x20 / 4) #define R_HASH_DEST (0x24 / 4) +#define R_HASH_KEY_BUFF (0x28 / 4) #define R_HASH_SRC_LEN (0x2c / 4) #define R_HASH_CMD (0x30 / 4) @@ -94,7 +96,8 @@ static int hash_algo_lookup(uint32_t reg) return -1; } -static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode) +static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode, + bool acc_mode) { struct iovec iov[ASPEED_HACE_MAX_SG]; g_autofree uint8_t *digest_buf; @@ -103,6 +106,7 @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode) if (sg_mode) { uint32_t len = 0; + uint32_t total_len = 0; for (i = 0; !(len & SG_LIST_LEN_LAST); i++) { uint32_t addr, src; @@ -123,10 +127,26 @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode) MEMTXATTRS_UNSPECIFIED, NULL); addr &= SG_LIST_ADDR_MASK; - iov[i].iov_len = len & SG_LIST_LEN_MASK; - plen = iov[i].iov_len; + plen = len & SG_LIST_LEN_MASK; iov[i].iov_base = address_space_map(&s->dram_as, addr, &plen, false, MEMTXATTRS_UNSPECIFIED); + + if (acc_mode) { + total_len += plen; + + if (len & SG_LIST_LEN_LAST) { + /* + * In the padding message, the last 64/128 bit represents + * the total length of bitstream in big endian. + * SHA-224, SHA-256 are 64 bit + * SHA-384, SHA-512, SHA-512/224, SHA-512/256 are 128 bit + * However, we would not process such a huge bit stream. + */ + plen -= total_len - (ldq_be_p(iov[i].iov_base + plen - 8) / 8); + } + } + + iov[i].iov_len = plen; } } else { hwaddr len = s->regs[R_HASH_SRC_LEN]; @@ -210,6 +230,9 @@ static void aspeed_hace_write(void *opaque, hwaddr addr, uint64_t data, case R_HASH_DEST: data &= ahc->dest_mask; break; + case R_HASH_KEY_BUFF: + data &= ahc->key_mask; + break; case R_HASH_SRC_LEN: data &= 0x0FFFFFFF; break; @@ -229,12 +252,13 @@ static void aspeed_hace_write(void *opaque, hwaddr addr, uint64_t data, } algo = hash_algo_lookup(data); if (algo < 0) { - qemu_log_mask(LOG_GUEST_ERROR, - "%s: Invalid hash algorithm selection 0x%"PRIx64"\n", - __func__, data & ahc->hash_mask); - break; + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Invalid hash algorithm selection 0x%"PRIx64"\n", + __func__, data & ahc->hash_mask); + break; } - do_hash_operation(s, algo, data & HASH_SG_EN); + do_hash_operation(s, algo, data & HASH_SG_EN, + ((data & HASH_HMAC_MASK) == HASH_DIGEST_ACCUM)); if (data & HASH_IRQ_EN) { qemu_irq_raise(s->irq); @@ -333,6 +357,7 @@ static void aspeed_ast2400_hace_class_init(ObjectClass *klass, void *data) ahc->src_mask = 0x0FFFFFFF; ahc->dest_mask = 0x0FFFFFF8; + ahc->key_mask = 0x0FFFFFC0; ahc->hash_mask = 0x000003ff; /* No SG or SHA512 modes */ } @@ -351,6 +376,7 @@ static void aspeed_ast2500_hace_class_init(ObjectClass *klass, void *data) ahc->src_mask = 0x3fffffff; ahc->dest_mask = 0x3ffffff8; + ahc->key_mask = 0x3FFFFFC0; ahc->hash_mask = 0x000003ff; /* No SG or SHA512 modes */ } @@ -369,6 +395,7 @@ static void aspeed_ast2600_hace_class_init(ObjectClass *klass, void *data) ahc->src_mask = 0x7FFFFFFF; ahc->dest_mask = 0x7FFFFFF8; + ahc->key_mask = 0x7FFFFFF8; ahc->hash_mask = 0x00147FFF; } diff --git a/include/hw/misc/aspeed_hace.h b/include/hw/misc/aspeed_hace.h index 94d5ada95f..2242945eb4 100644 --- a/include/hw/misc/aspeed_hace.h +++ b/include/hw/misc/aspeed_hace.h @@ -37,6 +37,7 @@ struct AspeedHACEClass { uint32_t src_mask; uint32_t dest_mask; + uint32_t key_mask; uint32_t hash_mask; }; -- 2.25.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v2 1/2] hw/misc: Supporting AST2600 HACE accumulative mode 2022-01-12 8:09 ` [PATCH v2 1/2] hw/misc: Supporting AST2600 HACE " Troy Lee @ 2022-01-12 8:12 ` Troy Lee 2022-01-17 8:11 ` Cédric Le Goater 2022-02-08 10:46 ` Joel Stanley 2 siblings, 0 replies; 9+ messages in thread From: Troy Lee @ 2022-01-12 8:12 UTC (permalink / raw) To: Troy Lee Cc: Peter Maydell, Andrew Jeffery, qemu-devel, hailin.wu, open list:ASPEED BMCs, Joel Stanley, Klaus Heinrich Kiwi, Cédric Le Goater [ Adding Klaus ] Sorry I forgot to add Klaus to the CC list. On Wed, Jan 12, 2022 at 4:10 PM Troy Lee <troy_lee@aspeedtech.com> wrote: > > Accumulative mode will supply a initial state and append padding bit at > the end of hash stream. However, the crypto library will padding those > bit automatically, so ripped it off from iov array. > > The aspeed ast2600 acculumative mode is described in datasheet > ast2600v10.pdf section 25.6.4: > 1. Allocationg and initiating accumulative hash digest write buffer > with initial state. > * Since QEMU crypto/hash api doesn't provide the API to set initial > state of hash library, and the initial state is already setted by > crypto library (gcrypt/glib/...), so skip this step. > 2. Calculating accumulative hash digest. > (a) When receiving the last accumulative data, software need to add > padding message at the end of the accumulative data. Padding > message described in specific of MD5, SHA-1, SHA224, SHA256, > SHA512, SHA512/224, SHA512/256. > * Since the crypto library (gcrypt/glib) already pad the > padding message internally. > * This patch is to remove the padding message which fed byguest > machine driver. > > Changes in v2: > - Coding style > - Add accumulative mode description in comment > > Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> > --- > hw/misc/aspeed_hace.c | 43 ++++++++++++++++++++++++++++------- > include/hw/misc/aspeed_hace.h | 1 + > 2 files changed, 36 insertions(+), 8 deletions(-) > > diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c > index 10f00e65f4..0710f44621 100644 > --- a/hw/misc/aspeed_hace.c > +++ b/hw/misc/aspeed_hace.c > @@ -11,6 +11,7 @@ > #include "qemu/osdep.h" > #include "qemu/log.h" > #include "qemu/error-report.h" > +#include "qemu/bswap.h" > #include "hw/misc/aspeed_hace.h" > #include "qapi/error.h" > #include "migration/vmstate.h" > @@ -27,6 +28,7 @@ > > #define R_HASH_SRC (0x20 / 4) > #define R_HASH_DEST (0x24 / 4) > +#define R_HASH_KEY_BUFF (0x28 / 4) > #define R_HASH_SRC_LEN (0x2c / 4) > > #define R_HASH_CMD (0x30 / 4) > @@ -94,7 +96,8 @@ static int hash_algo_lookup(uint32_t reg) > return -1; > } > > -static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode) > +static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode, > + bool acc_mode) > { > struct iovec iov[ASPEED_HACE_MAX_SG]; > g_autofree uint8_t *digest_buf; > @@ -103,6 +106,7 @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode) > > if (sg_mode) { > uint32_t len = 0; > + uint32_t total_len = 0; > > for (i = 0; !(len & SG_LIST_LEN_LAST); i++) { > uint32_t addr, src; > @@ -123,10 +127,26 @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode) > MEMTXATTRS_UNSPECIFIED, NULL); > addr &= SG_LIST_ADDR_MASK; > > - iov[i].iov_len = len & SG_LIST_LEN_MASK; > - plen = iov[i].iov_len; > + plen = len & SG_LIST_LEN_MASK; > iov[i].iov_base = address_space_map(&s->dram_as, addr, &plen, false, > MEMTXATTRS_UNSPECIFIED); > + > + if (acc_mode) { > + total_len += plen; > + > + if (len & SG_LIST_LEN_LAST) { > + /* > + * In the padding message, the last 64/128 bit represents > + * the total length of bitstream in big endian. > + * SHA-224, SHA-256 are 64 bit > + * SHA-384, SHA-512, SHA-512/224, SHA-512/256 are 128 bit > + * However, we would not process such a huge bit stream. > + */ > + plen -= total_len - (ldq_be_p(iov[i].iov_base + plen - 8) / 8); > + } > + } > + > + iov[i].iov_len = plen; > } > } else { > hwaddr len = s->regs[R_HASH_SRC_LEN]; > @@ -210,6 +230,9 @@ static void aspeed_hace_write(void *opaque, hwaddr addr, uint64_t data, > case R_HASH_DEST: > data &= ahc->dest_mask; > break; > + case R_HASH_KEY_BUFF: > + data &= ahc->key_mask; > + break; > case R_HASH_SRC_LEN: > data &= 0x0FFFFFFF; > break; > @@ -229,12 +252,13 @@ static void aspeed_hace_write(void *opaque, hwaddr addr, uint64_t data, > } > algo = hash_algo_lookup(data); > if (algo < 0) { > - qemu_log_mask(LOG_GUEST_ERROR, > - "%s: Invalid hash algorithm selection 0x%"PRIx64"\n", > - __func__, data & ahc->hash_mask); > - break; > + qemu_log_mask(LOG_GUEST_ERROR, > + "%s: Invalid hash algorithm selection 0x%"PRIx64"\n", > + __func__, data & ahc->hash_mask); > + break; > } > - do_hash_operation(s, algo, data & HASH_SG_EN); > + do_hash_operation(s, algo, data & HASH_SG_EN, > + ((data & HASH_HMAC_MASK) == HASH_DIGEST_ACCUM)); > > if (data & HASH_IRQ_EN) { > qemu_irq_raise(s->irq); > @@ -333,6 +357,7 @@ static void aspeed_ast2400_hace_class_init(ObjectClass *klass, void *data) > > ahc->src_mask = 0x0FFFFFFF; > ahc->dest_mask = 0x0FFFFFF8; > + ahc->key_mask = 0x0FFFFFC0; > ahc->hash_mask = 0x000003ff; /* No SG or SHA512 modes */ > } > > @@ -351,6 +376,7 @@ static void aspeed_ast2500_hace_class_init(ObjectClass *klass, void *data) > > ahc->src_mask = 0x3fffffff; > ahc->dest_mask = 0x3ffffff8; > + ahc->key_mask = 0x3FFFFFC0; > ahc->hash_mask = 0x000003ff; /* No SG or SHA512 modes */ > } > > @@ -369,6 +395,7 @@ static void aspeed_ast2600_hace_class_init(ObjectClass *klass, void *data) > > ahc->src_mask = 0x7FFFFFFF; > ahc->dest_mask = 0x7FFFFFF8; > + ahc->key_mask = 0x7FFFFFF8; > ahc->hash_mask = 0x00147FFF; > } > > diff --git a/include/hw/misc/aspeed_hace.h b/include/hw/misc/aspeed_hace.h > index 94d5ada95f..2242945eb4 100644 > --- a/include/hw/misc/aspeed_hace.h > +++ b/include/hw/misc/aspeed_hace.h > @@ -37,6 +37,7 @@ struct AspeedHACEClass { > > uint32_t src_mask; > uint32_t dest_mask; > + uint32_t key_mask; > uint32_t hash_mask; > }; > > -- > 2.25.1 > ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 1/2] hw/misc: Supporting AST2600 HACE accumulative mode 2022-01-12 8:09 ` [PATCH v2 1/2] hw/misc: Supporting AST2600 HACE " Troy Lee 2022-01-12 8:12 ` Troy Lee @ 2022-01-17 8:11 ` Cédric Le Goater 2022-01-17 8:48 ` Cédric Le Goater 2022-02-08 10:46 ` Joel Stanley 2 siblings, 1 reply; 9+ messages in thread From: Cédric Le Goater @ 2022-01-17 8:11 UTC (permalink / raw) To: Troy Lee, qemu-devel Cc: Peter Maydell, Andrew Jeffery, hailin.wu, leetroy, open list:ASPEED BMCs, Joel Stanley Hello Troy, On 1/12/22 09:09, Troy Lee wrote: > Accumulative mode will supply a initial state and append padding bit at > the end of hash stream. However, the crypto library will padding those > bit automatically, so ripped it off from iov array. > > The aspeed ast2600 acculumative mode is described in datasheet > ast2600v10.pdf section 25.6.4: > 1. Allocationg and initiating accumulative hash digest write buffer > with initial state. > * Since QEMU crypto/hash api doesn't provide the API to set initial > state of hash library, and the initial state is already setted by > crypto library (gcrypt/glib/...), so skip this step. > 2. Calculating accumulative hash digest. > (a) When receiving the last accumulative data, software need to add > padding message at the end of the accumulative data. Padding > message described in specific of MD5, SHA-1, SHA224, SHA256, > SHA512, SHA512/224, SHA512/256. > * Since the crypto library (gcrypt/glib) already pad the > padding message internally. > * This patch is to remove the padding message which fed byguest > machine driver. > > Changes in v2: > - Coding style > - Add accumulative mode description in comment > > Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> > --- > hw/misc/aspeed_hace.c | 43 ++++++++++++++++++++++++++++------- > include/hw/misc/aspeed_hace.h | 1 + > 2 files changed, 36 insertions(+), 8 deletions(-) > > diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c > index 10f00e65f4..0710f44621 100644 > --- a/hw/misc/aspeed_hace.c > +++ b/hw/misc/aspeed_hace.c > @@ -11,6 +11,7 @@ > #include "qemu/osdep.h" > #include "qemu/log.h" > #include "qemu/error-report.h" > +#include "qemu/bswap.h" > #include "hw/misc/aspeed_hace.h" > #include "qapi/error.h" > #include "migration/vmstate.h" > @@ -27,6 +28,7 @@ > > #define R_HASH_SRC (0x20 / 4) > #define R_HASH_DEST (0x24 / 4) > +#define R_HASH_KEY_BUFF (0x28 / 4) > #define R_HASH_SRC_LEN (0x2c / 4) > > #define R_HASH_CMD (0x30 / 4) > @@ -94,7 +96,8 @@ static int hash_algo_lookup(uint32_t reg) > return -1; > } > > -static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode) > +static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode, > + bool acc_mode) > { > struct iovec iov[ASPEED_HACE_MAX_SG]; > g_autofree uint8_t *digest_buf; > @@ -103,6 +106,7 @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode) > > if (sg_mode) { > uint32_t len = 0; > + uint32_t total_len = 0; > > for (i = 0; !(len & SG_LIST_LEN_LAST); i++) { > uint32_t addr, src; > @@ -123,10 +127,26 @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode) > MEMTXATTRS_UNSPECIFIED, NULL); > addr &= SG_LIST_ADDR_MASK; > > - iov[i].iov_len = len & SG_LIST_LEN_MASK; > - plen = iov[i].iov_len; > + plen = len & SG_LIST_LEN_MASK; > iov[i].iov_base = address_space_map(&s->dram_as, addr, &plen, false, > MEMTXATTRS_UNSPECIFIED); > + > + if (acc_mode) { > + total_len += plen; > + > + if (len & SG_LIST_LEN_LAST) { > + /* > + * In the padding message, the last 64/128 bit represents > + * the total length of bitstream in big endian. > + * SHA-224, SHA-256 are 64 bit > + * SHA-384, SHA-512, SHA-512/224, SHA-512/256 are 128 bit > + * However, we would not process such a huge bit stream. If we do not support accumulative mode with SHA-384, SHA-512, SHA-512/224, SHA-512/256 algos, we should make sure that do_hash_operation() is not called and emit a warning. Thanks, C. > + */ > + plen -= total_len - (ldq_be_p(iov[i].iov_base + plen - 8) / 8); > + } > + } > + > + iov[i].iov_len = plen; > } > } else { > hwaddr len = s->regs[R_HASH_SRC_LEN]; > @@ -210,6 +230,9 @@ static void aspeed_hace_write(void *opaque, hwaddr addr, uint64_t data, > case R_HASH_DEST: > data &= ahc->dest_mask; > break; > + case R_HASH_KEY_BUFF: > + data &= ahc->key_mask; > + break; > case R_HASH_SRC_LEN: > data &= 0x0FFFFFFF; > break; > @@ -229,12 +252,13 @@ static void aspeed_hace_write(void *opaque, hwaddr addr, uint64_t data, > } > algo = hash_algo_lookup(data); > if (algo < 0) { > - qemu_log_mask(LOG_GUEST_ERROR, > - "%s: Invalid hash algorithm selection 0x%"PRIx64"\n", > - __func__, data & ahc->hash_mask); > - break; > + qemu_log_mask(LOG_GUEST_ERROR, > + "%s: Invalid hash algorithm selection 0x%"PRIx64"\n", > + __func__, data & ahc->hash_mask); > + break; > } > - do_hash_operation(s, algo, data & HASH_SG_EN); > + do_hash_operation(s, algo, data & HASH_SG_EN, > + ((data & HASH_HMAC_MASK) == HASH_DIGEST_ACCUM)); > > if (data & HASH_IRQ_EN) { > qemu_irq_raise(s->irq); > @@ -333,6 +357,7 @@ static void aspeed_ast2400_hace_class_init(ObjectClass *klass, void *data) > > ahc->src_mask = 0x0FFFFFFF; > ahc->dest_mask = 0x0FFFFFF8; > + ahc->key_mask = 0x0FFFFFC0; > ahc->hash_mask = 0x000003ff; /* No SG or SHA512 modes */ > } > > @@ -351,6 +376,7 @@ static void aspeed_ast2500_hace_class_init(ObjectClass *klass, void *data) > > ahc->src_mask = 0x3fffffff; > ahc->dest_mask = 0x3ffffff8; > + ahc->key_mask = 0x3FFFFFC0; > ahc->hash_mask = 0x000003ff; /* No SG or SHA512 modes */ > } > > @@ -369,6 +395,7 @@ static void aspeed_ast2600_hace_class_init(ObjectClass *klass, void *data) > > ahc->src_mask = 0x7FFFFFFF; > ahc->dest_mask = 0x7FFFFFF8; > + ahc->key_mask = 0x7FFFFFF8; > ahc->hash_mask = 0x00147FFF; > } > > diff --git a/include/hw/misc/aspeed_hace.h b/include/hw/misc/aspeed_hace.h > index 94d5ada95f..2242945eb4 100644 > --- a/include/hw/misc/aspeed_hace.h > +++ b/include/hw/misc/aspeed_hace.h > @@ -37,6 +37,7 @@ struct AspeedHACEClass { > > uint32_t src_mask; > uint32_t dest_mask; > + uint32_t key_mask; > uint32_t hash_mask; > }; > > ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 1/2] hw/misc: Supporting AST2600 HACE accumulative mode 2022-01-17 8:11 ` Cédric Le Goater @ 2022-01-17 8:48 ` Cédric Le Goater 0 siblings, 0 replies; 9+ messages in thread From: Cédric Le Goater @ 2022-01-17 8:48 UTC (permalink / raw) To: Troy Lee, qemu-devel Cc: Peter Maydell, Andrew Jeffery, hailin.wu, leetroy, open list:ASPEED BMCs, Joel Stanley >> -static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode) >> +static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode, >> + bool acc_mode) >> { >> struct iovec iov[ASPEED_HACE_MAX_SG]; >> g_autofree uint8_t *digest_buf; >> @@ -103,6 +106,7 @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode) >> if (sg_mode) { >> uint32_t len = 0; >> + uint32_t total_len = 0; >> for (i = 0; !(len & SG_LIST_LEN_LAST); i++) { >> uint32_t addr, src; >> @@ -123,10 +127,26 @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode) >> MEMTXATTRS_UNSPECIFIED, NULL); >> addr &= SG_LIST_ADDR_MASK; >> - iov[i].iov_len = len & SG_LIST_LEN_MASK; >> - plen = iov[i].iov_len; >> + plen = len & SG_LIST_LEN_MASK; >> iov[i].iov_base = address_space_map(&s->dram_as, addr, &plen, false, >> MEMTXATTRS_UNSPECIFIED); >> + >> + if (acc_mode) { >> + total_len += plen; >> + >> + if (len & SG_LIST_LEN_LAST) { >> + /* >> + * In the padding message, the last 64/128 bit represents >> + * the total length of bitstream in big endian. >> + * SHA-224, SHA-256 are 64 bit >> + * SHA-384, SHA-512, SHA-512/224, SHA-512/256 are 128 bit >> + * However, we would not process such a huge bit stream. > > If we do not support accumulative mode with SHA-384, SHA-512, SHA-512/224, > SHA-512/256 algos, we should make sure that do_hash_operation() is not > called and emit a warning. I misunderstood the comment. I don't think it is very complex to extract the total length field correctly. You only need the algo type to pick the right size. May be add one more parameter to do_hash_operation() and >> + */ >> + plen -= total_len - (ldq_be_p(iov[i].iov_base + plen - 8) / 8); change the offset in the above ? Thanks, C. ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 1/2] hw/misc: Supporting AST2600 HACE accumulative mode 2022-01-12 8:09 ` [PATCH v2 1/2] hw/misc: Supporting AST2600 HACE " Troy Lee 2022-01-12 8:12 ` Troy Lee 2022-01-17 8:11 ` Cédric Le Goater @ 2022-02-08 10:46 ` Joel Stanley 2022-02-10 6:11 ` Troy Lee 2 siblings, 1 reply; 9+ messages in thread From: Joel Stanley @ 2022-02-08 10:46 UTC (permalink / raw) To: Troy Lee Cc: Peter Maydell, Andrew Jeffery, QEMU Developers, hailin.wu, leetroy, open list:ASPEED BMCs, Cédric Le Goater Hello Troy, On Wed, 12 Jan 2022 at 08:10, Troy Lee <troy_lee@aspeedtech.com> wrote: > > Accumulative mode will supply a initial state and append padding bit at > the end of hash stream. However, the crypto library will padding those > bit automatically, so ripped it off from iov array. > > The aspeed ast2600 acculumative mode is described in datasheet > ast2600v10.pdf section 25.6.4: > 1. Allocationg and initiating accumulative hash digest write buffer > with initial state. > * Since QEMU crypto/hash api doesn't provide the API to set initial > state of hash library, and the initial state is already setted by > crypto library (gcrypt/glib/...), so skip this step. > 2. Calculating accumulative hash digest. > (a) When receiving the last accumulative data, software need to add > padding message at the end of the accumulative data. Padding > message described in specific of MD5, SHA-1, SHA224, SHA256, > SHA512, SHA512/224, SHA512/256. > * Since the crypto library (gcrypt/glib) already pad the > padding message internally. > * This patch is to remove the padding message which fed byguest > machine driver. I tested the latest aspeed SDK u-boot, loaded form mmc (with our mmc model that lives in Cedric's tree) and qemu crashed: #0 0x00007fe867d44932 in ?? () from /usr/lib/x86_64-linux-gnu/libglib-2.0.so.0 #1 0x0000557aba2b6e22 in qcrypto_glib_hash_bytesv (alg=<optimized out>, iov=0x7fe8662ee0b0, niov=1, result=0x7fe8662ee0a8, resultlen=0x7fe8662ee0a0, errp=0x0) at ../crypto/hash-glib.c:68 #2 0x0000557ab9f549ea in do_hash_operation (s=s@entry=0x7fe866e1b3b0, algo=5, sg_mode=sg_mode@entry=true, acc_mode=acc_mode@entry=true) at ../hw/misc/aspeed_hace.c:161 #3 0x0000557ab9f54dd1 in aspeed_hace_write (opaque=<optimized out>, addr=12, data=262504, size=<optimized out>) at ../hw/misc/aspeed_hace.c:260 WIthout your patch applied the HACE operation fails, as we do not have support for accumulative mode, but we do not crash. > > Changes in v2: > - Coding style > - Add accumulative mode description in comment > > Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> > --- > hw/misc/aspeed_hace.c | 43 ++++++++++++++++++++++++++++------- > include/hw/misc/aspeed_hace.h | 1 + > 2 files changed, 36 insertions(+), 8 deletions(-) > > diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c > index 10f00e65f4..0710f44621 100644 > --- a/hw/misc/aspeed_hace.c > +++ b/hw/misc/aspeed_hace.c > @@ -11,6 +11,7 @@ > #include "qemu/osdep.h" > #include "qemu/log.h" > #include "qemu/error-report.h" > +#include "qemu/bswap.h" > #include "hw/misc/aspeed_hace.h" > #include "qapi/error.h" > #include "migration/vmstate.h" > @@ -27,6 +28,7 @@ > > #define R_HASH_SRC (0x20 / 4) > #define R_HASH_DEST (0x24 / 4) > +#define R_HASH_KEY_BUFF (0x28 / 4) > #define R_HASH_SRC_LEN (0x2c / 4) > > #define R_HASH_CMD (0x30 / 4) > @@ -94,7 +96,8 @@ static int hash_algo_lookup(uint32_t reg) > return -1; > } > > -static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode) > +static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode, > + bool acc_mode) > { > struct iovec iov[ASPEED_HACE_MAX_SG]; > g_autofree uint8_t *digest_buf; > @@ -103,6 +106,7 @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode) > > if (sg_mode) { > uint32_t len = 0; > + uint32_t total_len = 0; > > for (i = 0; !(len & SG_LIST_LEN_LAST); i++) { > uint32_t addr, src; > @@ -123,10 +127,26 @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode) > MEMTXATTRS_UNSPECIFIED, NULL); > addr &= SG_LIST_ADDR_MASK; > > - iov[i].iov_len = len & SG_LIST_LEN_MASK; > - plen = iov[i].iov_len; > + plen = len & SG_LIST_LEN_MASK; > iov[i].iov_base = address_space_map(&s->dram_as, addr, &plen, false, > MEMTXATTRS_UNSPECIFIED); > + > + if (acc_mode) { > + total_len += plen; > + > + if (len & SG_LIST_LEN_LAST) { > + /* > + * In the padding message, the last 64/128 bit represents > + * the total length of bitstream in big endian. > + * SHA-224, SHA-256 are 64 bit > + * SHA-384, SHA-512, SHA-512/224, SHA-512/256 are 128 bit > + * However, we would not process such a huge bit stream. > + */ > + plen -= total_len - (ldq_be_p(iov[i].iov_base + plen - 8) / 8); > + } > + } > + > + iov[i].iov_len = plen; > } > } else { > hwaddr len = s->regs[R_HASH_SRC_LEN]; > @@ -210,6 +230,9 @@ static void aspeed_hace_write(void *opaque, hwaddr addr, uint64_t data, > case R_HASH_DEST: > data &= ahc->dest_mask; > break; > + case R_HASH_KEY_BUFF: > + data &= ahc->key_mask; > + break; > case R_HASH_SRC_LEN: > data &= 0x0FFFFFFF; > break; > @@ -229,12 +252,13 @@ static void aspeed_hace_write(void *opaque, hwaddr addr, uint64_t data, > } > algo = hash_algo_lookup(data); > if (algo < 0) { > - qemu_log_mask(LOG_GUEST_ERROR, > - "%s: Invalid hash algorithm selection 0x%"PRIx64"\n", > - __func__, data & ahc->hash_mask); > - break; > + qemu_log_mask(LOG_GUEST_ERROR, > + "%s: Invalid hash algorithm selection 0x%"PRIx64"\n", > + __func__, data & ahc->hash_mask); > + break; > } > - do_hash_operation(s, algo, data & HASH_SG_EN); > + do_hash_operation(s, algo, data & HASH_SG_EN, > + ((data & HASH_HMAC_MASK) == HASH_DIGEST_ACCUM)); > > if (data & HASH_IRQ_EN) { > qemu_irq_raise(s->irq); > @@ -333,6 +357,7 @@ static void aspeed_ast2400_hace_class_init(ObjectClass *klass, void *data) > > ahc->src_mask = 0x0FFFFFFF; > ahc->dest_mask = 0x0FFFFFF8; > + ahc->key_mask = 0x0FFFFFC0; > ahc->hash_mask = 0x000003ff; /* No SG or SHA512 modes */ > } > > @@ -351,6 +376,7 @@ static void aspeed_ast2500_hace_class_init(ObjectClass *klass, void *data) > > ahc->src_mask = 0x3fffffff; > ahc->dest_mask = 0x3ffffff8; > + ahc->key_mask = 0x3FFFFFC0; > ahc->hash_mask = 0x000003ff; /* No SG or SHA512 modes */ > } > > @@ -369,6 +395,7 @@ static void aspeed_ast2600_hace_class_init(ObjectClass *klass, void *data) > > ahc->src_mask = 0x7FFFFFFF; > ahc->dest_mask = 0x7FFFFFF8; > + ahc->key_mask = 0x7FFFFFF8; > ahc->hash_mask = 0x00147FFF; > } > > diff --git a/include/hw/misc/aspeed_hace.h b/include/hw/misc/aspeed_hace.h > index 94d5ada95f..2242945eb4 100644 > --- a/include/hw/misc/aspeed_hace.h > +++ b/include/hw/misc/aspeed_hace.h > @@ -37,6 +37,7 @@ struct AspeedHACEClass { > > uint32_t src_mask; > uint32_t dest_mask; > + uint32_t key_mask; > uint32_t hash_mask; > }; > > -- > 2.25.1 > ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 1/2] hw/misc: Supporting AST2600 HACE accumulative mode 2022-02-08 10:46 ` Joel Stanley @ 2022-02-10 6:11 ` Troy Lee 0 siblings, 0 replies; 9+ messages in thread From: Troy Lee @ 2022-02-10 6:11 UTC (permalink / raw) To: Joel Stanley Cc: Peter Maydell, Andrew Jeffery, Troy Lee, QEMU Developers, hailin.wu, open list:ASPEED BMCs, Cédric Le Goater Hi Joel, On Tue, Feb 8, 2022 at 6:46 PM Joel Stanley <joel@jms.id.au> wrote: > > Hello Troy, > > On Wed, 12 Jan 2022 at 08:10, Troy Lee <troy_lee@aspeedtech.com> wrote: > > > > Accumulative mode will supply a initial state and append padding bit at > > the end of hash stream. However, the crypto library will padding those > > bit automatically, so ripped it off from iov array. > > > > The aspeed ast2600 acculumative mode is described in datasheet > > ast2600v10.pdf section 25.6.4: > > 1. Allocationg and initiating accumulative hash digest write buffer > > with initial state. > > * Since QEMU crypto/hash api doesn't provide the API to set initial > > state of hash library, and the initial state is already setted by > > crypto library (gcrypt/glib/...), so skip this step. > > 2. Calculating accumulative hash digest. > > (a) When receiving the last accumulative data, software need to add > > padding message at the end of the accumulative data. Padding > > message described in specific of MD5, SHA-1, SHA224, SHA256, > > SHA512, SHA512/224, SHA512/256. > > * Since the crypto library (gcrypt/glib) already pad the > > padding message internally. > > * This patch is to remove the padding message which fed byguest > > machine driver. > > > I tested the latest aspeed SDK u-boot, loaded form mmc (with our mmc > model that lives in Cedric's tree) and qemu crashed: > > #0 0x00007fe867d44932 in ?? () from /usr/lib/x86_64-linux-gnu/libglib-2.0.so.0 > #1 0x0000557aba2b6e22 in qcrypto_glib_hash_bytesv (alg=<optimized > out>, iov=0x7fe8662ee0b0, niov=1, result=0x7fe8662ee0a8, > resultlen=0x7fe8662ee0a0, errp=0x0) at ../crypto/hash-glib.c:68 > #2 0x0000557ab9f549ea in do_hash_operation (s=s@entry=0x7fe866e1b3b0, > algo=5, sg_mode=sg_mode@entry=true, acc_mode=acc_mode@entry=true) at > ../hw/misc/aspeed_hace.c:161 > #3 0x0000557ab9f54dd1 in aspeed_hace_write (opaque=<optimized out>, > addr=12, data=262504, size=<optimized out>) at > ../hw/misc/aspeed_hace.c:260 > > WIthout your patch applied the HACE operation fails, as we do not have > support for accumulative mode, but we do not crash. I'll double check on this issue. > > > > Changes in v2: > > - Coding style > > - Add accumulative mode description in comment > > > > Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> > > --- > > hw/misc/aspeed_hace.c | 43 ++++++++++++++++++++++++++++------- > > include/hw/misc/aspeed_hace.h | 1 + > > 2 files changed, 36 insertions(+), 8 deletions(-) > > > > diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c > > index 10f00e65f4..0710f44621 100644 > > --- a/hw/misc/aspeed_hace.c > > +++ b/hw/misc/aspeed_hace.c > > @@ -11,6 +11,7 @@ > > #include "qemu/osdep.h" > > #include "qemu/log.h" > > #include "qemu/error-report.h" > > +#include "qemu/bswap.h" > > #include "hw/misc/aspeed_hace.h" > > #include "qapi/error.h" > > #include "migration/vmstate.h" > > @@ -27,6 +28,7 @@ > > > > #define R_HASH_SRC (0x20 / 4) > > #define R_HASH_DEST (0x24 / 4) > > +#define R_HASH_KEY_BUFF (0x28 / 4) > > #define R_HASH_SRC_LEN (0x2c / 4) > > > > #define R_HASH_CMD (0x30 / 4) > > @@ -94,7 +96,8 @@ static int hash_algo_lookup(uint32_t reg) > > return -1; > > } > > > > -static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode) > > +static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode, > > + bool acc_mode) > > { > > struct iovec iov[ASPEED_HACE_MAX_SG]; > > g_autofree uint8_t *digest_buf; > > @@ -103,6 +106,7 @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode) > > > > if (sg_mode) { > > uint32_t len = 0; > > + uint32_t total_len = 0; > > > > for (i = 0; !(len & SG_LIST_LEN_LAST); i++) { > > uint32_t addr, src; > > @@ -123,10 +127,26 @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode) > > MEMTXATTRS_UNSPECIFIED, NULL); > > addr &= SG_LIST_ADDR_MASK; > > > > - iov[i].iov_len = len & SG_LIST_LEN_MASK; > > - plen = iov[i].iov_len; > > + plen = len & SG_LIST_LEN_MASK; > > iov[i].iov_base = address_space_map(&s->dram_as, addr, &plen, false, > > MEMTXATTRS_UNSPECIFIED); > > + > > + if (acc_mode) { > > + total_len += plen; > > + > > + if (len & SG_LIST_LEN_LAST) { > > + /* > > + * In the padding message, the last 64/128 bit represents > > + * the total length of bitstream in big endian. > > + * SHA-224, SHA-256 are 64 bit > > + * SHA-384, SHA-512, SHA-512/224, SHA-512/256 are 128 bit > > + * However, we would not process such a huge bit stream. > > + */ > > + plen -= total_len - (ldq_be_p(iov[i].iov_base + plen - 8) / 8); > > + } > > + } > > + > > + iov[i].iov_len = plen; > > } > > } else { > > hwaddr len = s->regs[R_HASH_SRC_LEN]; > > @@ -210,6 +230,9 @@ static void aspeed_hace_write(void *opaque, hwaddr addr, uint64_t data, > > case R_HASH_DEST: > > data &= ahc->dest_mask; > > break; > > + case R_HASH_KEY_BUFF: > > + data &= ahc->key_mask; > > + break; > > case R_HASH_SRC_LEN: > > data &= 0x0FFFFFFF; > > break; > > @@ -229,12 +252,13 @@ static void aspeed_hace_write(void *opaque, hwaddr addr, uint64_t data, > > } > > algo = hash_algo_lookup(data); > > if (algo < 0) { > > - qemu_log_mask(LOG_GUEST_ERROR, > > - "%s: Invalid hash algorithm selection 0x%"PRIx64"\n", > > - __func__, data & ahc->hash_mask); > > - break; > > + qemu_log_mask(LOG_GUEST_ERROR, > > + "%s: Invalid hash algorithm selection 0x%"PRIx64"\n", > > + __func__, data & ahc->hash_mask); > > + break; > > } > > - do_hash_operation(s, algo, data & HASH_SG_EN); > > + do_hash_operation(s, algo, data & HASH_SG_EN, > > + ((data & HASH_HMAC_MASK) == HASH_DIGEST_ACCUM)); > > > > if (data & HASH_IRQ_EN) { > > qemu_irq_raise(s->irq); > > @@ -333,6 +357,7 @@ static void aspeed_ast2400_hace_class_init(ObjectClass *klass, void *data) > > > > ahc->src_mask = 0x0FFFFFFF; > > ahc->dest_mask = 0x0FFFFFF8; > > + ahc->key_mask = 0x0FFFFFC0; > > ahc->hash_mask = 0x000003ff; /* No SG or SHA512 modes */ > > } > > > > @@ -351,6 +376,7 @@ static void aspeed_ast2500_hace_class_init(ObjectClass *klass, void *data) > > > > ahc->src_mask = 0x3fffffff; > > ahc->dest_mask = 0x3ffffff8; > > + ahc->key_mask = 0x3FFFFFC0; > > ahc->hash_mask = 0x000003ff; /* No SG or SHA512 modes */ > > } > > > > @@ -369,6 +395,7 @@ static void aspeed_ast2600_hace_class_init(ObjectClass *klass, void *data) > > > > ahc->src_mask = 0x7FFFFFFF; > > ahc->dest_mask = 0x7FFFFFF8; > > + ahc->key_mask = 0x7FFFFFF8; > > ahc->hash_mask = 0x00147FFF; > > } > > > > diff --git a/include/hw/misc/aspeed_hace.h b/include/hw/misc/aspeed_hace.h > > index 94d5ada95f..2242945eb4 100644 > > --- a/include/hw/misc/aspeed_hace.h > > +++ b/include/hw/misc/aspeed_hace.h > > @@ -37,6 +37,7 @@ struct AspeedHACEClass { > > > > uint32_t src_mask; > > uint32_t dest_mask; > > + uint32_t key_mask; > > uint32_t hash_mask; > > }; > > > > -- > > 2.25.1 > > ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 2/2] tests/qtest: Add test for Aspeed HACE accumulative mode 2022-01-12 8:09 [PATCH v2 0/2] Supporting AST2600 HACE engine accumulative mode Troy Lee 2022-01-12 8:09 ` [PATCH v2 1/2] hw/misc: Supporting AST2600 HACE " Troy Lee @ 2022-01-12 8:09 ` Troy Lee 2022-01-12 8:10 ` Troy Lee 1 sibling, 1 reply; 9+ messages in thread From: Troy Lee @ 2022-01-12 8:09 UTC (permalink / raw) To: qemu-devel Cc: Laurent Vivier, Peter Maydell, Thomas Huth, Andrew Jeffery, hailin.wu, leetroy, open list:ASPEED BMCs, Cédric Le Goater, Paolo Bonzini, Joel Stanley This add two addition test cases for accumulative mode under sg enabled. The input vector was manually craft with "abc" + bit 1 + padding zeros + L. The padding length depends on algorithm, i.e. SHA512 (1024 bit), SHA256 (512 bit). The result was calculated by command line sha512sum/sha256sum utilities without padding, i.e. only "abc" ascii text. Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> --- tests/qtest/aspeed_hace-test.c | 145 +++++++++++++++++++++++++++++++++ 1 file changed, 145 insertions(+) diff --git a/tests/qtest/aspeed_hace-test.c b/tests/qtest/aspeed_hace-test.c index 09ee31545e..6a2f404b93 100644 --- a/tests/qtest/aspeed_hace-test.c +++ b/tests/qtest/aspeed_hace-test.c @@ -21,6 +21,7 @@ #define HACE_ALGO_SHA512 (BIT(5) | BIT(6)) #define HACE_ALGO_SHA384 (BIT(5) | BIT(6) | BIT(10)) #define HACE_SG_EN BIT(18) +#define HACE_ACCUM_EN BIT(8) #define HACE_STS 0x1c #define HACE_RSA_ISR BIT(13) @@ -96,6 +97,57 @@ static const uint8_t test_result_sg_sha256[] = { 0x55, 0x1e, 0x1e, 0xc5, 0x80, 0xdd, 0x6d, 0x5a, 0x6e, 0xcd, 0xe9, 0xf3, 0xd3, 0x5e, 0x6e, 0x4a, 0x71, 0x7f, 0xbd, 0xe4}; +/* + * The accumulative mode requires firmware to provide internal initial state + * and message padding (including length L at the end of padding). + * + * This test vector is a ascii text "abc" with padding message. + * + * Expected results were generated using command line utitiles: + * + * echo -n -e 'abc' | dd of=/tmp/test + * for hash in sha512sum sha256sum; do $hash /tmp/test; done + */ +static const uint8_t test_vector_accum_512[] = { + 0x61, 0x62, 0x63, 0x80, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18}; + +static const uint8_t test_vector_accum_256[] = { + 0x61, 0x62, 0x63, 0x80, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18}; + +static const uint8_t test_result_accum_sha512[] = { + 0xdd, 0xaf, 0x35, 0xa1, 0x93, 0x61, 0x7a, 0xba, 0xcc, 0x41, 0x73, 0x49, + 0xae, 0x20, 0x41, 0x31, 0x12, 0xe6, 0xfa, 0x4e, 0x89, 0xa9, 0x7e, 0xa2, + 0x0a, 0x9e, 0xee, 0xe6, 0x4b, 0x55, 0xd3, 0x9a, 0x21, 0x92, 0x99, 0x2a, + 0x27, 0x4f, 0xc1, 0xa8, 0x36, 0xba, 0x3c, 0x23, 0xa3, 0xfe, 0xeb, 0xbd, + 0x45, 0x4d, 0x44, 0x23, 0x64, 0x3c, 0xe8, 0x0e, 0x2a, 0x9a, 0xc9, 0x4f, + 0xa5, 0x4c, 0xa4, 0x9f}; + +static const uint8_t test_result_accum_sha256[] = { + 0xba, 0x78, 0x16, 0xbf, 0x8f, 0x01, 0xcf, 0xea, 0x41, 0x41, 0x40, 0xde, + 0x5d, 0xae, 0x22, 0x23, 0xb0, 0x03, 0x61, 0xa3, 0x96, 0x17, 0x7a, 0x9c, + 0xb4, 0x10, 0xff, 0x61, 0xf2, 0x00, 0x15, 0xad}; static void write_regs(QTestState *s, uint32_t base, uint32_t src, uint32_t length, uint32_t out, uint32_t method) @@ -308,6 +360,86 @@ static void test_sha512_sg(const char *machine, const uint32_t base, qtest_quit(s); } +static void test_sha256_accum(const char *machine, const uint32_t base, + const uint32_t src_addr) +{ + QTestState *s = qtest_init(machine); + + const uint32_t buffer_addr = src_addr + 0x1000000; + const uint32_t digest_addr = src_addr + 0x4000000; + uint8_t digest[32] = {0}; + struct AspeedSgList array[] = { + { cpu_to_le32(sizeof(test_vector_accum_256) | SG_LIST_LEN_LAST), + cpu_to_le32(buffer_addr) }, + }; + + /* Check engine is idle, no busy or irq bits set */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); + + /* Write test vector into memory */ + qtest_memwrite(s, buffer_addr, test_vector_accum_256, sizeof(test_vector_accum_256)); + qtest_memwrite(s, src_addr, array, sizeof(array)); + + write_regs(s, base, src_addr, sizeof(test_vector_accum_256), + digest_addr, HACE_ALGO_SHA256 | HACE_SG_EN | HACE_ACCUM_EN); + + /* Check hash IRQ status is asserted */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200); + + /* Clear IRQ status and check status is deasserted */ + qtest_writel(s, base + HACE_STS, 0x00000200); + g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); + + /* Read computed digest from memory */ + qtest_memread(s, digest_addr, digest, sizeof(digest)); + + /* Check result of computation */ + g_assert_cmpmem(digest, sizeof(digest), + test_result_accum_sha256, sizeof(digest)); + + qtest_quit(s); +} + +static void test_sha512_accum(const char *machine, const uint32_t base, + const uint32_t src_addr) +{ + QTestState *s = qtest_init(machine); + + const uint32_t buffer_addr = src_addr + 0x1000000; + const uint32_t digest_addr = src_addr + 0x4000000; + uint8_t digest[64] = {0}; + struct AspeedSgList array[] = { + { cpu_to_le32(sizeof(test_vector_accum_512) | SG_LIST_LEN_LAST), + cpu_to_le32(buffer_addr) }, + }; + + /* Check engine is idle, no busy or irq bits set */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); + + /* Write test vector into memory */ + qtest_memwrite(s, buffer_addr, test_vector_accum_512, sizeof(test_vector_accum_512)); + qtest_memwrite(s, src_addr, array, sizeof(array)); + + write_regs(s, base, src_addr, sizeof(test_vector_accum_512), + digest_addr, HACE_ALGO_SHA512 | HACE_SG_EN | HACE_ACCUM_EN); + + /* Check hash IRQ status is asserted */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200); + + /* Clear IRQ status and check status is deasserted */ + qtest_writel(s, base + HACE_STS, 0x00000200); + g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); + + /* Read computed digest from memory */ + qtest_memread(s, digest_addr, digest, sizeof(digest)); + + /* Check result of computation */ + g_assert_cmpmem(digest, sizeof(digest), + test_result_accum_sha512, sizeof(digest)); + + qtest_quit(s); +} + struct masks { uint32_t src; uint32_t dest; @@ -396,6 +528,16 @@ static void test_sha512_sg_ast2600(void) test_sha512_sg("-machine ast2600-evb", 0x1e6d0000, 0x80000000); } +static void test_sha256_accum_ast2600(void) +{ + test_sha256_accum("-machine ast2600-evb", 0x1e6d0000, 0x80000000); +} + +static void test_sha512_accum_ast2600(void) +{ + test_sha512_accum("-machine ast2600-evb", 0x1e6d0000, 0x80000000); +} + static void test_addresses_ast2600(void) { test_addresses("-machine ast2600-evb", 0x1e6d0000, &ast2600_masks); @@ -455,6 +597,9 @@ int main(int argc, char **argv) qtest_add_func("ast2600/hace/sha512_sg", test_sha512_sg_ast2600); qtest_add_func("ast2600/hace/sha256_sg", test_sha256_sg_ast2600); + qtest_add_func("ast2600/hace/sha512_accum", test_sha512_accum_ast2600); + qtest_add_func("ast2600/hace/sha256_accum", test_sha256_accum_ast2600); + qtest_add_func("ast2500/hace/addresses", test_addresses_ast2500); qtest_add_func("ast2500/hace/sha512", test_sha512_ast2500); qtest_add_func("ast2500/hace/sha256", test_sha256_ast2500); -- 2.25.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v2 2/2] tests/qtest: Add test for Aspeed HACE accumulative mode 2022-01-12 8:09 ` [PATCH v2 2/2] tests/qtest: Add test for Aspeed " Troy Lee @ 2022-01-12 8:10 ` Troy Lee 0 siblings, 0 replies; 9+ messages in thread From: Troy Lee @ 2022-01-12 8:10 UTC (permalink / raw) To: Troy Lee Cc: Laurent Vivier, Peter Maydell, Thomas Huth, Andrew Jeffery, qemu-devel, hailin.wu, open list:ASPEED BMCs, Joel Stanley, Paolo Bonzini, Klaus Heinrich Kiwi, Cédric Le Goater [ Adding Klaus ] On Wed, Jan 12, 2022 at 4:09 PM Troy Lee <troy_lee@aspeedtech.com> wrote: > > This add two addition test cases for accumulative mode under sg enabled. > > The input vector was manually craft with "abc" + bit 1 + padding zeros + L. > The padding length depends on algorithm, i.e. SHA512 (1024 bit), > SHA256 (512 bit). > > The result was calculated by command line sha512sum/sha256sum utilities > without padding, i.e. only "abc" ascii text. > > Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> > --- > tests/qtest/aspeed_hace-test.c | 145 +++++++++++++++++++++++++++++++++ > 1 file changed, 145 insertions(+) > > diff --git a/tests/qtest/aspeed_hace-test.c b/tests/qtest/aspeed_hace-test.c > index 09ee31545e..6a2f404b93 100644 > --- a/tests/qtest/aspeed_hace-test.c > +++ b/tests/qtest/aspeed_hace-test.c > @@ -21,6 +21,7 @@ > #define HACE_ALGO_SHA512 (BIT(5) | BIT(6)) > #define HACE_ALGO_SHA384 (BIT(5) | BIT(6) | BIT(10)) > #define HACE_SG_EN BIT(18) > +#define HACE_ACCUM_EN BIT(8) > > #define HACE_STS 0x1c > #define HACE_RSA_ISR BIT(13) > @@ -96,6 +97,57 @@ static const uint8_t test_result_sg_sha256[] = { > 0x55, 0x1e, 0x1e, 0xc5, 0x80, 0xdd, 0x6d, 0x5a, 0x6e, 0xcd, 0xe9, 0xf3, > 0xd3, 0x5e, 0x6e, 0x4a, 0x71, 0x7f, 0xbd, 0xe4}; > > +/* > + * The accumulative mode requires firmware to provide internal initial state > + * and message padding (including length L at the end of padding). > + * > + * This test vector is a ascii text "abc" with padding message. > + * > + * Expected results were generated using command line utitiles: > + * > + * echo -n -e 'abc' | dd of=/tmp/test > + * for hash in sha512sum sha256sum; do $hash /tmp/test; done > + */ > +static const uint8_t test_vector_accum_512[] = { > + 0x61, 0x62, 0x63, 0x80, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18}; > + > +static const uint8_t test_vector_accum_256[] = { > + 0x61, 0x62, 0x63, 0x80, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18}; > + > +static const uint8_t test_result_accum_sha512[] = { > + 0xdd, 0xaf, 0x35, 0xa1, 0x93, 0x61, 0x7a, 0xba, 0xcc, 0x41, 0x73, 0x49, > + 0xae, 0x20, 0x41, 0x31, 0x12, 0xe6, 0xfa, 0x4e, 0x89, 0xa9, 0x7e, 0xa2, > + 0x0a, 0x9e, 0xee, 0xe6, 0x4b, 0x55, 0xd3, 0x9a, 0x21, 0x92, 0x99, 0x2a, > + 0x27, 0x4f, 0xc1, 0xa8, 0x36, 0xba, 0x3c, 0x23, 0xa3, 0xfe, 0xeb, 0xbd, > + 0x45, 0x4d, 0x44, 0x23, 0x64, 0x3c, 0xe8, 0x0e, 0x2a, 0x9a, 0xc9, 0x4f, > + 0xa5, 0x4c, 0xa4, 0x9f}; > + > +static const uint8_t test_result_accum_sha256[] = { > + 0xba, 0x78, 0x16, 0xbf, 0x8f, 0x01, 0xcf, 0xea, 0x41, 0x41, 0x40, 0xde, > + 0x5d, 0xae, 0x22, 0x23, 0xb0, 0x03, 0x61, 0xa3, 0x96, 0x17, 0x7a, 0x9c, > + 0xb4, 0x10, 0xff, 0x61, 0xf2, 0x00, 0x15, 0xad}; > > static void write_regs(QTestState *s, uint32_t base, uint32_t src, > uint32_t length, uint32_t out, uint32_t method) > @@ -308,6 +360,86 @@ static void test_sha512_sg(const char *machine, const uint32_t base, > qtest_quit(s); > } > > +static void test_sha256_accum(const char *machine, const uint32_t base, > + const uint32_t src_addr) > +{ > + QTestState *s = qtest_init(machine); > + > + const uint32_t buffer_addr = src_addr + 0x1000000; > + const uint32_t digest_addr = src_addr + 0x4000000; > + uint8_t digest[32] = {0}; > + struct AspeedSgList array[] = { > + { cpu_to_le32(sizeof(test_vector_accum_256) | SG_LIST_LEN_LAST), > + cpu_to_le32(buffer_addr) }, > + }; > + > + /* Check engine is idle, no busy or irq bits set */ > + g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); > + > + /* Write test vector into memory */ > + qtest_memwrite(s, buffer_addr, test_vector_accum_256, sizeof(test_vector_accum_256)); > + qtest_memwrite(s, src_addr, array, sizeof(array)); > + > + write_regs(s, base, src_addr, sizeof(test_vector_accum_256), > + digest_addr, HACE_ALGO_SHA256 | HACE_SG_EN | HACE_ACCUM_EN); > + > + /* Check hash IRQ status is asserted */ > + g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200); > + > + /* Clear IRQ status and check status is deasserted */ > + qtest_writel(s, base + HACE_STS, 0x00000200); > + g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); > + > + /* Read computed digest from memory */ > + qtest_memread(s, digest_addr, digest, sizeof(digest)); > + > + /* Check result of computation */ > + g_assert_cmpmem(digest, sizeof(digest), > + test_result_accum_sha256, sizeof(digest)); > + > + qtest_quit(s); > +} > + > +static void test_sha512_accum(const char *machine, const uint32_t base, > + const uint32_t src_addr) > +{ > + QTestState *s = qtest_init(machine); > + > + const uint32_t buffer_addr = src_addr + 0x1000000; > + const uint32_t digest_addr = src_addr + 0x4000000; > + uint8_t digest[64] = {0}; > + struct AspeedSgList array[] = { > + { cpu_to_le32(sizeof(test_vector_accum_512) | SG_LIST_LEN_LAST), > + cpu_to_le32(buffer_addr) }, > + }; > + > + /* Check engine is idle, no busy or irq bits set */ > + g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); > + > + /* Write test vector into memory */ > + qtest_memwrite(s, buffer_addr, test_vector_accum_512, sizeof(test_vector_accum_512)); > + qtest_memwrite(s, src_addr, array, sizeof(array)); > + > + write_regs(s, base, src_addr, sizeof(test_vector_accum_512), > + digest_addr, HACE_ALGO_SHA512 | HACE_SG_EN | HACE_ACCUM_EN); > + > + /* Check hash IRQ status is asserted */ > + g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200); > + > + /* Clear IRQ status and check status is deasserted */ > + qtest_writel(s, base + HACE_STS, 0x00000200); > + g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); > + > + /* Read computed digest from memory */ > + qtest_memread(s, digest_addr, digest, sizeof(digest)); > + > + /* Check result of computation */ > + g_assert_cmpmem(digest, sizeof(digest), > + test_result_accum_sha512, sizeof(digest)); > + > + qtest_quit(s); > +} > + > struct masks { > uint32_t src; > uint32_t dest; > @@ -396,6 +528,16 @@ static void test_sha512_sg_ast2600(void) > test_sha512_sg("-machine ast2600-evb", 0x1e6d0000, 0x80000000); > } > > +static void test_sha256_accum_ast2600(void) > +{ > + test_sha256_accum("-machine ast2600-evb", 0x1e6d0000, 0x80000000); > +} > + > +static void test_sha512_accum_ast2600(void) > +{ > + test_sha512_accum("-machine ast2600-evb", 0x1e6d0000, 0x80000000); > +} > + > static void test_addresses_ast2600(void) > { > test_addresses("-machine ast2600-evb", 0x1e6d0000, &ast2600_masks); > @@ -455,6 +597,9 @@ int main(int argc, char **argv) > qtest_add_func("ast2600/hace/sha512_sg", test_sha512_sg_ast2600); > qtest_add_func("ast2600/hace/sha256_sg", test_sha256_sg_ast2600); > > + qtest_add_func("ast2600/hace/sha512_accum", test_sha512_accum_ast2600); > + qtest_add_func("ast2600/hace/sha256_accum", test_sha256_accum_ast2600); > + > qtest_add_func("ast2500/hace/addresses", test_addresses_ast2500); > qtest_add_func("ast2500/hace/sha512", test_sha512_ast2500); > qtest_add_func("ast2500/hace/sha256", test_sha256_ast2500); > -- > 2.25.1 > ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2022-02-10 6:16 UTC | newest] Thread overview: 9+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2022-01-12 8:09 [PATCH v2 0/2] Supporting AST2600 HACE engine accumulative mode Troy Lee 2022-01-12 8:09 ` [PATCH v2 1/2] hw/misc: Supporting AST2600 HACE " Troy Lee 2022-01-12 8:12 ` Troy Lee 2022-01-17 8:11 ` Cédric Le Goater 2022-01-17 8:48 ` Cédric Le Goater 2022-02-08 10:46 ` Joel Stanley 2022-02-10 6:11 ` Troy Lee 2022-01-12 8:09 ` [PATCH v2 2/2] tests/qtest: Add test for Aspeed " Troy Lee 2022-01-12 8:10 ` Troy Lee
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