From: "Cédric Le Goater" <clg@redhat.com>
To: Aditya Gupta <adityag@linux.ibm.com>,
Nicholas Piggin <npiggin@gmail.com>,
Harsh Prateek Bora <harshpb@linux.ibm.com>
Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com>,
Madhavan Srinivasan <maddy@linux.ibm.com>,
Gautam Menghani <gautam@linux.ibm.com>,
Mike Kowal <kowal@linux.ibm.com>,
Miles Glenn <milesg@linux.ibm.com>,
Ganesh Goudar <ganeshgr@linux.ibm.com>,
qemu-devel@nongnu.org, qemu-ppc@nongnu.org
Subject: Re: [PATCH v10 3/8] ppc/pnv: Add PnvChipClass handler to get reference to interrupt controller
Date: Thu, 25 Sep 2025 23:02:03 +0200 [thread overview]
Message-ID: <9bfc50c6-1bb2-4e94-bf8b-98ae2a33540f@redhat.com> (raw)
In-Reply-To: <20250925173049.891406-4-adityag@linux.ibm.com>
On 9/25/25 19:30, Aditya Gupta wrote:
> Existing code in XIVE2 assumes the chip to be a Power10 Chip.
> Instead add a handler to get reference to the interrupt controller (XIVE)
> for a given Power Chip.
>
> Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Thanks,
C.
> ---
> hw/intc/pnv_xive2.c | 4 ++--
> hw/ppc/pnv.c | 12 ++++++++++++
> include/hw/ppc/pnv_chip.h | 1 +
> 3 files changed, 15 insertions(+), 2 deletions(-)
>
> diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c
> index e019cad5c14c..0663baab544c 100644
> --- a/hw/intc/pnv_xive2.c
> +++ b/hw/intc/pnv_xive2.c
> @@ -110,8 +110,8 @@ static PnvXive2 *pnv_xive2_get_remote(uint32_t vsd_type, hwaddr fwd_addr)
> int i;
>
> for (i = 0; i < pnv->num_chips; i++) {
> - Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]);
> - PnvXive2 *xive = &chip10->xive;
> + PnvChipClass *k = PNV_CHIP_GET_CLASS(pnv->chips[i]);
> + PnvXive2 *xive = PNV_XIVE2(k->intc_get(pnv->chips[i]));
>
> /*
> * Is this the XIVE matching the forwarded VSD address is for this
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index 423954ba7e0c..a4fdf59207fa 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -1486,6 +1486,16 @@ static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
> xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf);
> }
>
> +static void *pnv_chip_power10_intc_get(PnvChip *chip)
> +{
> + return &PNV10_CHIP(chip)->xive;
> +}
> +
> +static void *pnv_chip_power11_intc_get(PnvChip *chip)
> +{
> + return &PNV11_CHIP(chip)->xive;
> +}
> +
> /*
> * Allowed core identifiers on a POWER8 Processor Chip :
> *
> @@ -2680,6 +2690,7 @@ static void pnv_chip_power10_class_init(ObjectClass *klass, const void *data)
> k->intc_reset = pnv_chip_power10_intc_reset;
> k->intc_destroy = pnv_chip_power10_intc_destroy;
> k->intc_print_info = pnv_chip_power10_intc_print_info;
> + k->intc_get = pnv_chip_power10_intc_get;
> k->isa_create = pnv_chip_power10_isa_create;
> k->dt_populate = pnv_chip_power10_dt_populate;
> k->pic_print_info = pnv_chip_power10_pic_print_info;
> @@ -2709,6 +2720,7 @@ static void pnv_chip_power11_class_init(ObjectClass *klass, const void *data)
> k->chip_cfam_id = 0x220da04980000000ull; /* P11 DD2.0 (with NX) */
> k->cores_mask = POWER11_CORE_MASK;
> k->get_pir_tir = pnv_get_pir_tir_p10;
> + k->intc_get = pnv_chip_power11_intc_get;
> k->isa_create = pnv_chip_power11_isa_create;
> k->dt_populate = pnv_chip_power11_dt_populate;
> k->pic_print_info = pnv_chip_power11_pic_print_info;
> diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h
> index 6bd930f8b439..a5b8c49680d3 100644
> --- a/include/hw/ppc/pnv_chip.h
> +++ b/include/hw/ppc/pnv_chip.h
> @@ -170,6 +170,7 @@ struct PnvChipClass {
> void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu);
> void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu);
> void (*intc_print_info)(PnvChip *chip, PowerPCCPU *cpu, GString *buf);
> + void* (*intc_get)(PnvChip *chip);
> ISABus *(*isa_create)(PnvChip *chip, Error **errp);
> void (*dt_populate)(PnvChip *chip, void *fdt);
> void (*pic_print_info)(PnvChip *chip, GString *buf);
next prev parent reply other threads:[~2025-09-25 21:04 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-25 17:30 [PATCH v10 0/8] Power11 support for QEMU [PowerNV] Aditya Gupta
2025-09-25 17:30 ` [PATCH v10 1/8] ppc/pnv: Introduce Pnv11Chip Aditya Gupta
2025-10-06 15:45 ` Mike Kowal
2025-10-06 18:24 ` Aditya Gupta
2025-10-07 5:40 ` Cédric Le Goater
2025-09-25 17:30 ` [PATCH v10 2/8] ppc/pnv: Introduce Power11 PowerNV machine Aditya Gupta
2025-10-06 15:45 ` Mike Kowal
2025-09-25 17:30 ` [PATCH v10 3/8] ppc/pnv: Add PnvChipClass handler to get reference to interrupt controller Aditya Gupta
2025-09-25 21:02 ` Cédric Le Goater [this message]
2025-09-27 13:25 ` Aditya Gupta
2025-10-06 15:46 ` Mike Kowal
2025-09-25 17:30 ` [PATCH v10 4/8] ppc/pnv: Add XIVE2 controller to Power11 Aditya Gupta
2025-10-06 15:46 ` Mike Kowal
2025-09-25 17:30 ` [PATCH v10 5/8] ppc/pnv: Add PHB5 PCIe Host bridge " Aditya Gupta
2025-10-06 15:47 ` Mike Kowal
2025-09-25 17:30 ` [PATCH v10 6/8] ppc/pnv: Add ChipTOD model for Power11 Aditya Gupta
2025-10-06 15:47 ` Mike Kowal
2025-09-25 17:30 ` [PATCH v10 7/8] tests/powernv: Switch to buildroot images instead of op-build Aditya Gupta
2025-09-25 17:30 ` [PATCH v10 8/8] tests/powernv: Add PowerNV test for Power11 Aditya Gupta
2025-09-25 21:12 ` [PATCH v10 0/8] Power11 support for QEMU [PowerNV] Cédric Le Goater
2025-09-27 13:28 ` Aditya Gupta
2025-09-28 16:34 ` Amit Machhiwal
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=9bfc50c6-1bb2-4e94-bf8b-98ae2a33540f@redhat.com \
--to=clg@redhat.com \
--cc=adityag@linux.ibm.com \
--cc=ganeshgr@linux.ibm.com \
--cc=gautam@linux.ibm.com \
--cc=harshpb@linux.ibm.com \
--cc=kowal@linux.ibm.com \
--cc=maddy@linux.ibm.com \
--cc=mahesh@linux.ibm.com \
--cc=milesg@linux.ibm.com \
--cc=npiggin@gmail.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-ppc@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).