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[88.21.102.131]) by smtp.gmail.com with ESMTPSA id p25sm3085995wma.20.2019.11.22.03.48.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 22 Nov 2019 03:48:21 -0800 (PST) Subject: Re: [PATCH v35 09/13] target/avr: Add instruction translation - CPU main translation function To: Michael Rolnik , qemu-devel@nongnu.org References: <20191029212430.20617-1-mrolnik@gmail.com> <20191029212430.20617-10-mrolnik@gmail.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <9c36b2d2-fea1-0cb5-dbea-49af8ec6c7e3@redhat.com> Date: Fri, 22 Nov 2019 12:48:20 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.1.1 MIME-Version: 1.0 In-Reply-To: <20191029212430.20617-10-mrolnik@gmail.com> Content-Language: en-US X-MC-Unique: rB_XHrWEM6iSOP-7sC-RTA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: thuth@redhat.com, Joaquin de Andres , richard.henderson@linaro.org, dovgaluk@ispras.ru, imammedo@redhat.com, aleksandar.m.mail@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 10/29/19 10:24 PM, Michael Rolnik wrote: > Co-developed-by: Richard Henderson This misses a: "Signed-off-by: Richard Henderson " > Co-developed-by: Michael Rolnik >=20 > Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daud=C3=A9 > --- > target/avr/translate.c | 234 +++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 234 insertions(+) >=20 > diff --git a/target/avr/translate.c b/target/avr/translate.c > index 30ba13bdd7..fdf4e11f58 100644 > --- a/target/avr/translate.c > +++ b/target/avr/translate.c > @@ -2792,3 +2792,237 @@ static bool trans_WDR(DisasContext *ctx, arg_WDR = *a) > =20 > return true; > } > + > + > +void avr_cpu_tcg_init(void) > +{ > + int i; > + > +#define AVR_REG_OFFS(x) offsetof(CPUAVRState, x) > + cpu_pc =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(pc_w), "pc")= ; > + cpu_Cf =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregC), "Cf"= ); > + cpu_Zf =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregZ), "Zf"= ); > + cpu_Nf =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregN), "Nf"= ); > + cpu_Vf =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregV), "Vf"= ); > + cpu_Sf =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregS), "Sf"= ); > + cpu_Hf =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregH), "Hf"= ); > + cpu_Tf =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregT), "Tf"= ); > + cpu_If =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregI), "If"= ); > + cpu_rampD =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampD), "= rampD"); > + cpu_rampX =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampX), "= rampX"); > + cpu_rampY =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampY), "= rampY"); > + cpu_rampZ =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampZ), "= rampZ"); > + cpu_eind =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(eind), "ei= nd"); > + cpu_sp =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sp), "sp"); > + cpu_skip =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(skip), "sk= ip"); > + > + for (i =3D 0; i < NO_CPU_REGISTERS; i++) { > + cpu_r[i] =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(r[i]), > + reg_names[i]); > + } > +#undef AVR_REG_OFFS > +} > + > +static void translate(DisasContext *ctx) > +{ > + uint32_t opcode =3D next_word(ctx); > + > + if (!decode_insn(ctx, opcode)) { > + gen_helper_unsupported(cpu_env); > + ctx->bstate =3D DISAS_NORETURN; > + } > +} > + > +/* Standardize the cpu_skip condition to NE. */ > +static bool canonicalize_skip(DisasContext *ctx) > +{ > + switch (ctx->skip_cond) { > + case TCG_COND_NEVER: > + /* Normal case: cpu_skip is known to be false. */ > + return false; > + > + case TCG_COND_ALWAYS: > + /* > + * Breakpoint case: cpu_skip is known to be true, via TB_FLAGS_S= KIP. > + * The breakpoint is on the instruction being skipped, at the st= art > + * of the TranslationBlock. No need to update. > + */ > + return false; > + > + case TCG_COND_NE: > + if (ctx->skip_var1 =3D=3D NULL) { > + tcg_gen_mov_tl(cpu_skip, ctx->skip_var0); > + } else { > + tcg_gen_xor_tl(cpu_skip, ctx->skip_var0, ctx->skip_var1); > + ctx->skip_var1 =3D NULL; > + } > + break; > + > + default: > + /* Convert to a NE condition vs 0. */ > + if (ctx->skip_var1 =3D=3D NULL) { > + tcg_gen_setcondi_tl(ctx->skip_cond, cpu_skip, ctx->skip_var0= , 0); > + } else { > + tcg_gen_setcond_tl(ctx->skip_cond, cpu_skip, > + ctx->skip_var0, ctx->skip_var1); > + ctx->skip_var1 =3D NULL; > + } > + ctx->skip_cond =3D TCG_COND_NE; > + break; > + } > + if (ctx->free_skip_var0) { > + tcg_temp_free(ctx->skip_var0); > + ctx->free_skip_var0 =3D false; > + } > + ctx->skip_var0 =3D cpu_skip; > + return true; > +} > + > +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_i= nsns) > +{ > + CPUAVRState *env =3D cs->env_ptr; > + DisasContext ctx =3D { > + .tb =3D tb, > + .cs =3D cs, > + .env =3D env, > + .memidx =3D 0, > + .bstate =3D DISAS_NEXT, > + .skip_cond =3D TCG_COND_NEVER, > + .singlestep =3D cs->singlestep_enabled, > + }; > + target_ulong pc_start =3D tb->pc / 2; > + int num_insns =3D 0; > + > + if (tb->flags & TB_FLAGS_FULL_ACCESS) { > + /* > + * This flag is set by ST/LD instruction we will regenerate it O= NLY > + * with mem/cpu memory access instead of mem access > + */ > + max_insns =3D 1; > + } > + if (ctx.singlestep) { > + max_insns =3D 1; > + } > + > + gen_tb_start(tb); > + > + ctx.npc =3D pc_start; > + if (tb->flags & TB_FLAGS_SKIP) { > + ctx.skip_cond =3D TCG_COND_ALWAYS; > + ctx.skip_var0 =3D cpu_skip; > + } > + > + do { > + TCGLabel *skip_label =3D NULL; > + > + /* translate current instruction */ > + tcg_gen_insn_start(ctx.npc); > + num_insns++; > + > + /* > + * this is due to some strange GDB behavior > + * let's assume main has address 0x100 > + * b main - sets breakpoint at address 0x00000100 (code) > + * b *0x100 - sets breakpoint at address 0x00800100 (data) > + */ > + if (unlikely(!ctx.singlestep && > + (cpu_breakpoint_test(cs, OFFSET_CODE + ctx.npc * 2, BP_A= NY) || > + cpu_breakpoint_test(cs, OFFSET_DATA + ctx.npc * 2, BP_A= NY)))) { > + canonicalize_skip(&ctx); > + tcg_gen_movi_tl(cpu_pc, ctx.npc); > + gen_helper_debug(cpu_env); > + goto done_generating; > + } > + > + /* Conditionally skip the next instruction, if indicated. */ > + if (ctx.skip_cond !=3D TCG_COND_NEVER) { > + skip_label =3D gen_new_label(); > + if (ctx.skip_var0 =3D=3D cpu_skip) { > + /* > + * Copy cpu_skip so that we may zero it before the branc= h. > + * This ensures that cpu_skip is non-zero after the labe= l > + * if and only if the skipped insn itself sets a skip. > + */ > + ctx.free_skip_var0 =3D true; > + ctx.skip_var0 =3D tcg_temp_new(); > + tcg_gen_mov_tl(ctx.skip_var0, cpu_skip); > + tcg_gen_movi_tl(cpu_skip, 0); > + } > + if (ctx.skip_var1 =3D=3D NULL) { > + tcg_gen_brcondi_tl(ctx.skip_cond, ctx.skip_var0, 0, skip= _label); > + } else { > + tcg_gen_brcond_tl(ctx.skip_cond, ctx.skip_var0, > + ctx.skip_var1, skip_label); > + ctx.skip_var1 =3D NULL; > + } > + if (ctx.free_skip_var0) { > + tcg_temp_free(ctx.skip_var0); > + ctx.free_skip_var0 =3D false; > + } > + ctx.skip_cond =3D TCG_COND_NEVER; > + ctx.skip_var0 =3D NULL; > + } > + > + translate(&ctx); > + > + if (skip_label) { > + canonicalize_skip(&ctx); > + gen_set_label(skip_label); > + if (ctx.bstate =3D=3D DISAS_NORETURN) { > + ctx.bstate =3D DISAS_CHAIN; > + } > + } > + } while (ctx.bstate =3D=3D DISAS_NEXT > + && num_insns < max_insns > + && (ctx.npc - pc_start) * 2 < TARGET_PAGE_SIZE - 4 > + && !tcg_op_buf_full()); > + > + if (tb->cflags & CF_LAST_IO) { > + gen_io_end(); > + } > + > + bool nonconst_skip =3D canonicalize_skip(&ctx); > + > + switch (ctx.bstate) { > + case DISAS_NORETURN: > + assert(!nonconst_skip); > + break; > + case DISAS_NEXT: > + case DISAS_TOO_MANY: > + case DISAS_CHAIN: > + if (!nonconst_skip) { > + /* Note gen_goto_tb checks singlestep. */ > + gen_goto_tb(&ctx, 1, ctx.npc); > + break; > + } > + tcg_gen_movi_tl(cpu_pc, ctx.npc); > + /* fall through */ > + case DISAS_LOOKUP: > + if (!ctx.singlestep) { > + tcg_gen_lookup_and_goto_ptr(); > + break; > + } > + /* fall through */ > + case DISAS_EXIT: > + if (ctx.singlestep) { > + gen_helper_debug(cpu_env); > + } else { > + tcg_gen_exit_tb(NULL, 0); > + } > + break; > + default: > + g_assert_not_reached(); > + } > + > +done_generating: > + gen_tb_end(tb, num_insns); > + > + tb->size =3D (ctx.npc - pc_start) * 2; > + tb->icount =3D num_insns; > +} > + > +void restore_state_to_opc(CPUAVRState *env, TranslationBlock *tb, > + target_ulong *data) > +{ > + env->pc_w =3D data[0]; > +} >=20