From: Richard Henderson <richard.henderson@linaro.org>
To: "Frédéric Pétrot" <frederic.petrot@univ-grenoble-alpes.fr>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: philmd@redhat.com, bin.meng@windriver.com,
alistair.francis@wdc.com, palmer@dabbelt.com,
fabien.portas@grenoble-inp.org
Subject: Re: [PATCH v3 08/21] target/riscv: adding accessors to the registers upper part
Date: Wed, 20 Oct 2021 08:09:13 -0700 [thread overview]
Message-ID: <9c3ade01-e5e0-a1e6-a39d-73d5cccdd0b8@linaro.org> (raw)
In-Reply-To: <20211019094812.614056-9-frederic.petrot@univ-grenoble-alpes.fr>
On 10/19/21 2:47 AM, Frédéric Pétrot wrote:
> +static TCGv get_gprh(DisasContext *ctx, int reg_num)
> +{
> + if (reg_num == 0 || get_ol(ctx) < MXL_RV128) {
> + return ctx->zero;
> + }
So... why return anything for OL < 128?
Seems like that should be a bug.
> +static void gen_set_gprh(DisasContext *ctx, int reg_num, TCGv t)
> +{
> + if (reg_num != 0) {
> + if (get_ol(ctx) < MXL_RV128) {
> + tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63);
> + } else {
> + tcg_gen_mov_tl(cpu_gprh[reg_num], t);
> + }
> + }
Hmm... this implies that you must set the low part first, which could be easy to mis-use.
Probably better to create a combined gen_set_gpr128 that takes both halves at once.
> + /* devilish temporary code so that the patch compiles */
> + if (get_xl_max(ctx) == MXL_RV128) {
> + (void)get_gprh(ctx, 6);
> + (void)dest_gprh(ctx, 6);
> + gen_set_gprh(ctx, 6, NULL);
> + }
I don't think it would be confusing to squash this patch into the next one, which adds the
actual uses.
r~
next prev parent reply other threads:[~2021-10-20 15:13 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-19 9:47 [PATCH v3 00/21] Adding partial support for 128-bit riscv target Frédéric Pétrot
2021-10-19 9:47 ` [PATCH v3 01/21] memory: change define name for consistency Frédéric Pétrot
2021-10-20 15:07 ` Philippe Mathieu-Daudé
2021-10-19 9:47 ` [PATCH v3 02/21] memory: add a few defines for octo (128-bit) values Frédéric Pétrot
2021-10-19 18:00 ` Richard Henderson
2021-10-19 9:47 ` [PATCH v3 03/21] Int128.h: addition of a few 128-bit operations Frédéric Pétrot
2021-10-19 18:15 ` Richard Henderson
2021-10-19 9:47 ` [PATCH v3 04/21] target/riscv: additional macros to check instruction support Frédéric Pétrot
2021-10-20 14:08 ` Richard Henderson
2021-10-21 16:22 ` Frédéric Pétrot
2021-10-19 9:47 ` [PATCH v3 05/21] target/riscv: separation of bitwise logic and aritmetic helpers Frédéric Pétrot
2021-10-20 14:14 ` Richard Henderson
2021-10-19 9:47 ` [PATCH v3 06/21] target/riscv: array for the 64 upper bits of 128-bit registers Frédéric Pétrot
2021-10-20 14:44 ` Richard Henderson
2021-10-22 6:06 ` Frédéric Pétrot
2021-10-19 9:47 ` [PATCH v3 07/21] target/riscv: setup everything so that riscv128-softmmu compiles Frédéric Pétrot
2021-10-20 14:57 ` Richard Henderson
2021-10-19 9:47 ` [PATCH v3 08/21] target/riscv: adding accessors to the registers upper part Frédéric Pétrot
2021-10-20 15:09 ` Richard Henderson [this message]
2021-10-19 9:48 ` [PATCH v3 09/21] target/riscv: moving some insns close to similar insns Frédéric Pétrot
2021-10-20 15:11 ` Richard Henderson
2021-10-19 9:48 ` [PATCH v3 10/21] target/riscv: support for 128-bit loads and store Frédéric Pétrot
2021-10-20 17:31 ` Richard Henderson
2021-10-19 9:48 ` [PATCH v3 11/21] target/riscv: support for 128-bit bitwise instructions Frédéric Pétrot
2021-10-20 17:47 ` Richard Henderson
2021-10-20 19:18 ` Frédéric Pétrot
2021-10-19 9:48 ` [PATCH v3 12/21] target/riscv: support for 128-bit U-type instructions Frédéric Pétrot
2021-10-20 17:59 ` Richard Henderson
2021-10-19 9:48 ` [PATCH v3 13/21] target/riscv: support for 128-bit shift instructions Frédéric Pétrot
2021-10-20 19:06 ` Richard Henderson
2021-10-24 22:49 ` Frédéric Pétrot
2021-10-19 9:48 ` [PATCH v3 14/21] target/riscv: support for 128-bit arithmetic instructions Frédéric Pétrot
2021-10-20 20:15 ` Richard Henderson
2021-10-19 9:48 ` [PATCH v3 15/21] target/riscv: support for 128-bit M extension Frédéric Pétrot
2021-10-20 20:58 ` Richard Henderson
2021-10-19 9:48 ` [PATCH v3 16/21] target/riscv: adding high part of some csrs Frédéric Pétrot
2021-10-20 21:38 ` Richard Henderson
2021-10-20 23:03 ` Richard Henderson
2021-10-19 9:48 ` [PATCH v3 17/21] target/riscv: helper functions to wrap calls to 128-bit csr insns Frédéric Pétrot
2021-10-20 21:47 ` Richard Henderson
2021-10-19 9:48 ` [PATCH v3 18/21] target/riscv: modification of the trans_csrxx for 128-bit support Frédéric Pétrot
2021-10-20 21:53 ` Richard Henderson
2021-10-19 9:48 ` [PATCH v3 19/21] target/riscv: actual functions to realize crs 128-bit insns Frédéric Pétrot
2021-10-20 22:18 ` Richard Henderson
2021-10-19 9:48 ` [PATCH v3 20/21] target/riscv: adding 128-bit access functions for some csrs Frédéric Pétrot
2021-10-20 23:18 ` Richard Henderson
2021-10-19 9:48 ` [PATCH v3 21/21] target/riscv: support for 128-bit satp Frédéric Pétrot
2021-10-20 23:09 ` Richard Henderson
2021-10-21 11:12 ` Frédéric Pétrot
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