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[88.10.102.251]) by smtp.gmail.com with ESMTPSA id b144sm4735801wmb.3.2019.09.06.00.12.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 06 Sep 2019 00:12:34 -0700 (PDT) To: Richard Henderson , qemu-devel@nongnu.org References: <20190820210720.18976-1-richard.henderson@linaro.org> <20190820210720.18976-14-richard.henderson@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Openpgp: id=89C1E78F601EE86C867495CBA2A3FD6EDEADC0DE; url=http://pgp.mit.edu/pks/lookup?op=get&search=0xA2A3FD6EDEADC0DE Message-ID: <9c3d3506-ca1a-2bc9-174e-d981d3e067b5@redhat.com> Date: Fri, 6 Sep 2019 09:12:33 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 MIME-Version: 1.0 In-Reply-To: <20190820210720.18976-14-richard.henderson@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: Re: [Qemu-devel] [PATCH v5 13/17] target/arm: Split out arm_mmu_idx_el X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 8/20/19 11:07 PM, Richard Henderson wrote: > Avoid calling arm_current_el() twice. >=20 > Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 > --- > target/arm/internals.h | 9 +++++++++ > target/arm/helper.c | 12 +++++++----- > 2 files changed, 16 insertions(+), 5 deletions(-) >=20 > diff --git a/target/arm/internals.h b/target/arm/internals.h > index 232d963875..f5313dd3d4 100644 > --- a/target/arm/internals.h > +++ b/target/arm/internals.h > @@ -949,6 +949,15 @@ void arm_cpu_update_virq(ARMCPU *cpu); > */ > void arm_cpu_update_vfiq(ARMCPU *cpu); > =20 > +/** > + * arm_mmu_idx_el: > + * @env: The cpu environment > + * @el: The EL to use. > + * > + * Return the full ARMMMUIdx for the translation regime for EL. > + */ > +ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el); > + > /** > * arm_mmu_idx: > * @env: The cpu environment > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 83ae33dae5..19bdb9b9d6 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -10988,15 +10988,12 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARM= State *env, bool secstate) > } > #endif > =20 > -ARMMMUIdx arm_mmu_idx(CPUARMState *env) > +ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) > { > - int el; > - > if (arm_feature(env, ARM_FEATURE_M)) { > return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); > } > =20 > - el =3D arm_current_el(env); > if (el < 2 && arm_is_secure_below_el3(env)) { > return ARMMMUIdx_S1SE0 + el; > } else { > @@ -11004,6 +11001,11 @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env) > } > } > =20 > +ARMMMUIdx arm_mmu_idx(CPUARMState *env) > +{ > + return arm_mmu_idx_el(env, arm_current_el(env)); > +} > + > int cpu_mmu_index(CPUARMState *env, bool ifetch) > { > return arm_to_core_mmu_idx(arm_mmu_idx(env)); > @@ -11164,7 +11166,7 @@ static uint32_t rebuild_hflags_internal(CPUARMS= tate *env) > { > int el =3D arm_current_el(env); > int fp_el =3D fp_exception_el(env, el); > - ARMMMUIdx mmu_idx =3D arm_mmu_idx(env); > + ARMMMUIdx mmu_idx =3D arm_mmu_idx_el(env, el); > =20 > if (is_a64(env)) { > return rebuild_hflags_a64(env, el, fp_el, mmu_idx); >=20