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Fri, 09 Feb 2024 01:15:30 -0800 (PST) Message-ID: <9c40cbb8-c652-409f-a718-b6381b96ba89@linaro.org> Date: Fri, 9 Feb 2024 10:15:27 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 7/8] mips: allow compiling out CONFIG_MIPS_ITU Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= To: Paolo Bonzini Cc: qemu-devel@nongnu.org, shentey@gmail.com, Richard Henderson , Peter Maydell References: <20240207111411.115040-1-pbonzini@redhat.com> <20240207111411.115040-8-pbonzini@redhat.com> <81d117a3-ed1d-4023-a9ce-128729ec2e73@linaro.org> <75ede98a-db0d-4b8c-88ff-df2f46875466@linaro.org> In-Reply-To: <75ede98a-db0d-4b8c-88ff-df2f46875466@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::134; envelope-from=philmd@linaro.org; helo=mail-lf1-x134.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 9/2/24 08:22, Philippe Mathieu-Daudé wrote: > On 8/2/24 09:26, Paolo Bonzini wrote: >> On Wed, Feb 7, 2024 at 8:12 PM Philippe Mathieu-Daudé >> wrote: >>> >>> Hi Paolo, >>> >>> On 7/2/24 12:14, Paolo Bonzini wrote: >>>> itc_reconfigure() is referenced from TCG, provide a stub if needed. >>>> This makes it possible to build a QEMU binary that only includes >>>> boards without a CPS device (only Malta and Boston create one). >>>> >>>> Signed-off-by: Paolo Bonzini >>>> --- >>>>    hw/mips/mips_itu-stub.c | 26 ++++++++++++++++++++++++++ >>>>    hw/mips/meson.build     |  1 + >>>>    2 files changed, 27 insertions(+) >>>>    create mode 100644 hw/mips/mips_itu-stub.c >>>> >>>> diff --git a/hw/mips/mips_itu-stub.c b/hw/mips/mips_itu-stub.c >>>> new file mode 100644 >>>> index 00000000000..4cc82b8461f >>>> --- /dev/null >>>> +++ b/hw/mips/mips_itu-stub.c >>>> @@ -0,0 +1,26 @@ >>>> +/* >>>> + * Inter-Thread Communication Unit emulation. >>>> + * >>>> + * Copyright (c) 2016 Imagination Technologies >>>> + * >>>> + * This library is free software; you can redistribute it and/or >>>> + * modify it under the terms of the GNU Lesser General Public >>>> + * License as published by the Free Software Foundation; either >>>> + * version 2.1 of the License, or (at your option) any later version. >>>> + * >>>> + * This library is distributed in the hope that it will be useful, >>>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU >>>> + * Lesser General Public License for more details. >>>> + * >>>> + * You should have received a copy of the GNU Lesser General Public >>>> + * License along with this library; if not, see >>>> . >>> >>> This is your code addition, so "Inter-Thread Communication Unit stubs" / >>> RH / SPDX GPLv2-or-later. >>> >>>> + */ >>>> + >>>> +#include "qemu/osdep.h" >>>> +#include "hw/misc/mips_itu.h" >>>> + >>>> +void itc_reconfigure(MIPSITUState *tag) >>>> +{ >>>> +    abort(); >>> >>> As Zoltan suggested, g_assert_not_reached(). Indeed this path >>> can't be reached without ITU, TCG won't emit anything and will >>> call instead: >>> >>>       qemu_log_mask(LOG_UNIMP, "mthc0 %s (reg %d sel %d)\n", >>>                     register_name, reg, sel); >>> >>> I'm reluctant to add stubs, but since it helps you (hoping we >>> can figure a clean way to split architectural access to hw/ from >>> tcg/ one day): >> >> Not sure how it's reached anyway, because the saar field of >> DisasContext is never written... Alternatively: https://lore.kernel.org/qemu-devel/20240209090513.9401-3-philmd@linaro.org/ > Commit 5fb2dcd179 ("target/mips: Provide R/W access to SAARI > and SAAR CP0 registers") is an incomplete frontport of > https://github.com/MIPS/qemu/commit/c9340491cc. > > Commit 043715d1e0 ("target/mips: Update ITU to utilize SAARI > and SAAR CP0 registers") is an incomplete frontport of > https://github.com/MIPS/qemu/commit/e03079c699. > > So this feature is working in MIPS fork since 2017, and during > 2019 mainstream only got part of it merged but never completed. > > 5 years passed.