From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com
Subject: [Qemu-devel] [PATCH v1 24/27] target/riscv: Allow specifying number of MMU stages
Date: Fri, 7 Jun 2019 14:56:36 -0700 [thread overview]
Message-ID: <9c5428112ee1ecd12de27a0d95ff08f9f9feb428.1559944445.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1559944445.git.alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 6cef78a2c7..6ff4272da2 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -286,7 +286,7 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
static int get_physical_address(CPURISCVState *env, hwaddr *physical,
int *prot, target_ulong addr,
int access_type, int mmu_idx,
- bool first_stage)
+ bool first_stage, bool two_stage)
{
/* NOTE: the env->pc value visible here will not be
* correct, but the value visible to the exception handler
@@ -518,9 +518,10 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
int mmu_idx = cpu_mmu_index(&cpu->env, false);
if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0, mmu_idx,
- true)) {
+ true, false)) {
return -1;
}
+
return phys_addr;
}
@@ -579,7 +580,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
__func__, address, access_type, mmu_idx);
ret = get_physical_address(env, &pa, &prot, address, access_type, mmu_idx,
- true);
+ true, false);
qemu_log_mask(CPU_LOG_MMU,
"%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx
--
2.21.0
next prev parent reply other threads:[~2019-06-07 22:18 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-07 21:55 [Qemu-devel] [PATCH v1 00/27] Add RISC-V Hypervisor Extension Alistair Francis
2019-06-07 21:55 ` [Qemu-devel] [PATCH v1 01/27] target/riscv: Don't set write permissions on dirty PTEs Alistair Francis
2019-06-07 21:55 ` [Qemu-devel] [PATCH v1 02/27] target/riscv: Add the Hypervisor extension Alistair Francis
2019-06-07 21:55 ` [Qemu-devel] [PATCH v1 03/27] target/riscv: Add the virtulisation mode Alistair Francis
2019-06-07 21:55 ` [Qemu-devel] [PATCH v1 04/27] target/riscv: Add the force HS exception mode Alistair Francis
2019-06-07 21:55 ` [Qemu-devel] [PATCH v1 05/27] target/riscv: Add the Hypervisor CSRs to CPUState Alistair Francis
2019-06-07 21:55 ` [Qemu-devel] [PATCH v1 06/27] target/riscv: Dump Hypervisor registers if enabled Alistair Francis
2019-06-07 21:55 ` [Qemu-devel] [PATCH v1 07/27] target/riscv: Remove strict perm checking for CSR R/W Alistair Francis
2019-06-07 21:55 ` [Qemu-devel] [PATCH v1 08/27] target/riscv: Create function to test if FP is enabled Alistair Francis
2019-06-07 21:55 ` [Qemu-devel] [PATCH v1 09/27] target/riscv: Add support for background interrupt setting Alistair Francis
2019-06-07 21:55 ` [Qemu-devel] [PATCH v1 10/27] target/riscv: Add Hypervisor CSR access functions Alistair Francis
2019-06-07 21:55 ` [Qemu-devel] [PATCH v1 11/27] target/riscv: Add background CSRs accesses Alistair Francis
2019-06-07 21:55 ` [Qemu-devel] [PATCH v1 12/27] target/riscv: Add background register swapping function Alistair Francis
2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 13/27] target/ricsv: Flush the TLB on virtulisation mode changes Alistair Francis
2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 14/27] target/riscv: Generate illegal instruction on WFI when V=1 Alistair Francis
2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 15/27] riscv: plic: Remove unused interrupt functions Alistair Francis
2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 16/27] riscv: plic: Always set sip.SEIP bit for HS Alistair Francis
2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 17/27] target/riscv: Add hypvervisor trap support Alistair Francis
2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 18/27] target/riscv: Add Hypervisor trap return support Alistair Francis
2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 19/27] target/riscv: Add hfence instructions Alistair Francis
2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 20/27] target/riscv: Disable guest FP support based on backgrond status Alistair Francis
2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 21/27] target/riscv: Mark both sstatus and bsstatus as dirty Alistair Francis
2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 22/27] target/riscv: Respect MPRV and SPRV for floating point ops Alistair Francis
2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 23/27] target/riscv: Allow specifying MMU stage Alistair Francis
2019-06-07 21:56 ` Alistair Francis [this message]
2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 25/27] target/riscv: Implement second stage MMU Alistair Francis
2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 26/27] target/riscv: Call the second stage MMU in virtualisation mode Alistair Francis
2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 27/27] target/riscv: Allow enabling the Hypervisor extension Alistair Francis
2019-07-15 11:50 ` [Qemu-devel] [PATCH v1 00/27] Add RISC-V Hypervisor Extension Chih-Min Chao
2019-07-17 0:13 ` Alistair Francis
2019-07-15 11:59 ` Peter Maydell
2019-07-17 0:14 ` Alistair Francis
2019-07-17 3:55 ` Chih-Min Chao
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