From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: Michael Clark <mjc@sifive.com>, qemu-devel@nongnu.org
Cc: Palmer Dabbelt <palmer@sifive.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
RISC-V Patches <patches@groups.riscv.org>
Subject: Re: [Qemu-devel] [PATCH v7 08/23] RISC-V TCG Code Generation
Date: Tue, 27 Feb 2018 15:06:24 +0100 [thread overview]
Message-ID: <9c743e0d-73f6-5972-77dc-ed07ed86953c@mail.uni-paderborn.de> (raw)
In-Reply-To: <1519683480-33201-9-git-send-email-mjc@sifive.com>
On 02/26/2018 11:17 PM, Michael Clark wrote:
> TCG code generation for the RV32IMAFDC and RV64IMAFDC. The QEMU
> RISC-V code generator has complete coverage for the Base ISA v2.2,
> Privileged ISA v1.9.1 and Privileged ISA v1.10:
>
> - RISC-V Instruction Set Manual Volume I: User-Level ISA Version 2.2
> - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.9.1
> - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.10
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Michael Clark <mjc@sifive.com>
> ---
> target/riscv/instmap.h | 364 +++++++++
> target/riscv/translate.c | 1974 ++++++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 2338 insertions(+)
> create mode 100644 target/riscv/instmap.h
> create mode 100644 target/riscv/translate.c
>
Since I contributed here and Peter wants all the relevant SoB's, here is
mine:
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cheers,
Bastian
next prev parent reply other threads:[~2018-02-27 14:09 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-26 22:17 [Qemu-devel] [PATCH v7 00/23] RISC-V QEMU Port Submission Michael Clark
2018-02-26 22:17 ` [Qemu-devel] [PATCH v7 01/23] RISC-V Maintainers Michael Clark
2018-02-26 22:17 ` [Qemu-devel] [PATCH v7 02/23] RISC-V ELF Machine Definition Michael Clark
2018-02-26 22:17 ` [Qemu-devel] [PATCH v7 03/23] RISC-V CPU Core Definition Michael Clark
2018-02-26 22:17 ` [Qemu-devel] [PATCH v7 04/23] RISC-V Disassembler Michael Clark
2018-02-26 22:17 ` [Qemu-devel] [PATCH v7 05/23] RISC-V CPU Helpers Michael Clark
2018-02-26 22:17 ` [Qemu-devel] [PATCH v7 06/23] RISC-V FPU Support Michael Clark
2018-02-26 22:17 ` [Qemu-devel] [PATCH v7 07/23] RISC-V GDB Stub Michael Clark
2018-02-26 22:17 ` [Qemu-devel] [PATCH v7 08/23] RISC-V TCG Code Generation Michael Clark
2018-02-27 14:06 ` Bastian Koppelmann [this message]
2018-02-26 22:17 ` [Qemu-devel] [PATCH v7 09/23] RISC-V Physical Memory Protection Michael Clark
2018-02-26 22:17 ` [Qemu-devel] [PATCH v7 10/23] RISC-V Linux User Emulation Michael Clark
2018-02-26 22:17 ` [Qemu-devel] [PATCH v7 11/23] Add symbol table callback interface to load_elf Michael Clark
2018-02-26 22:17 ` [Qemu-devel] [PATCH v7 12/23] RISC-V HTIF Console Michael Clark
2018-02-26 22:17 ` [Qemu-devel] [PATCH v7 13/23] RISC-V HART Array Michael Clark
2018-02-26 22:17 ` [Qemu-devel] [PATCH v7 14/23] SiFive RISC-V CLINT Block Michael Clark
2018-02-26 22:17 ` [Qemu-devel] [PATCH v7 15/23] SiFive RISC-V PLIC Block Michael Clark
2018-02-26 22:17 ` [Qemu-devel] [PATCH v7 16/23] RISC-V Spike Machines Michael Clark
2018-02-26 22:17 ` [Qemu-devel] [PATCH v7 17/23] SiFive RISC-V Test Finisher Michael Clark
2018-02-26 22:17 ` [Qemu-devel] [PATCH v7 18/23] RISC-V VirtIO Machine Michael Clark
2018-02-26 22:17 ` [Qemu-devel] [PATCH v7 19/23] SiFive RISC-V UART Device Michael Clark
2018-02-26 22:17 ` [Qemu-devel] [PATCH v7 20/23] SiFive RISC-V PRCI Block Michael Clark
2018-02-26 22:17 ` [Qemu-devel] [PATCH v7 21/23] SiFive Freedom E300 RISC-V Machine Michael Clark
2018-02-26 22:17 ` [Qemu-devel] [PATCH v7 22/23] SiFive Freedom U500 " Michael Clark
2018-02-26 22:18 ` [Qemu-devel] [PATCH v7 23/23] RISC-V Build Infrastructure Michael Clark
2018-02-26 23:02 ` Eric Blake
2018-02-26 22:24 ` [Qemu-devel] [PATCH v7 00/23] RISC-V QEMU Port Submission Michael Clark
2018-02-26 23:05 ` Eric Blake
2018-02-26 22:45 ` no-reply
2018-02-26 22:57 ` no-reply
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