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From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-ID: <9c743e0d-73f6-5972-77dc-ed07ed86953c@mail.uni-paderborn.de>
Date: Tue, 27 Feb 2018 15:06:24 +0100
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Subject: Re: [Qemu-devel] [PATCH v7 08/23] RISC-V TCG Code Generation
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To: Michael Clark <mjc@sifive.com>, qemu-devel@nongnu.org
Cc: Palmer Dabbelt <palmer@sifive.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>, RISC-V Patches <patches@groups.riscv.org>

On 02/26/2018 11:17 PM, Michael Clark wrote:
> TCG code generation for the RV32IMAFDC and RV64IMAFDC. The QEMU
> RISC-V code generator has complete coverage for the Base ISA v2.2,
> Privileged ISA v1.9.1 and Privileged ISA v1.10:
> 
> - RISC-V Instruction Set Manual Volume I: User-Level ISA Version 2.2
> - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.9.1
> - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.10
> 
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Michael Clark <mjc@sifive.com>
> ---
>  target/riscv/instmap.h   |  364 +++++++++
>  target/riscv/translate.c | 1974 ++++++++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 2338 insertions(+)
>  create mode 100644 target/riscv/instmap.h
>  create mode 100644 target/riscv/translate.c
> 

Since I contributed here and Peter wants all the relevant SoB's, here is
mine:

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>

Cheers,
Bastian