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Thu, 15 May 2025 15:55:51 +0000 (GMT) Message-ID: <9c7a76a72952ce19f326077c54c865e72e0bbe06.camel@linux.ibm.com> Subject: Re: [PATCH 31/50] ppc/xive: Fix high prio group interrupt being preempted by low prio VP From: Miles Glenn To: Nicholas Piggin , qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, =?ISO-8859-1?Q?Fr=E9d=E9ric?= Barrat , Michael Kowal , Caleb Schlossin Date: Thu, 15 May 2025 10:55:51 -0500 In-Reply-To: <20250512031100.439842-32-npiggin@gmail.com> References: <20250512031100.439842-1-npiggin@gmail.com> <20250512031100.439842-32-npiggin@gmail.com> Organization: IBM Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5 (3.28.5-27.el8_10) Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: clCdyxuT007p0MHkOwbeULlMpbcZFpev X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE1MDE1NSBTYWx0ZWRfXxT1qV0wSOurA syMRpVXamfDH6UtL7gNJxBAXh0Ab7tjfjt/6f+6DHdg918ho4IxxZUIJp3xMqWvuICUGTaa05MC FEpwDIM7iM4m5B4HKjMrIFH4HA95n5zvfbBgZp8UZXrMwxiuxr8SdTgArlBGzmubniCCndDzbi3 m8hLNDUJq5lj2LEZ4cpqxIn0b/yB2KWdrMmmgmafZ+M6FYpZBd3ZRjwnqGjtMhS3fXcQNrbfKLl 3a4ycXbMHMc2VW42/hIP7pdjqQJCTopZ4T3vmMKcfjEhT+fX9KlPP5KIJ67NqYFncmd7+2qeThs EhL0QsKY3O1/KFTBAyXNN5tSwKMYMDLxyNyDb7NmC0hbu89wbrGc7v7LKtzv7BkpZ1Fb4wLq8zU qPx51QkdbHDtkPpe5XbMC7y+athRUPNUhy3OsANzwlvuDuFPSVGl/6P2XaXEaHs8MBIZVHsP X-Proofpoint-ORIG-GUID: h02dHfwycbpZEk-a2O04KUS7R4Kfv1Wl X-Authority-Analysis: v=2.4 cv=OsNPyz/t c=1 sm=1 tr=0 ts=68260e8b cx=c_pps a=bLidbwmWQ0KltjZqbj+ezA==:117 a=bLidbwmWQ0KltjZqbj+ezA==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=VnNF1IyMAAAA:8 a=pGLkceISAAAA:8 a=jbdF2D7wSZ7cY4eH8r0A:9 a=QEXdDO2ut3YA:10 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-15_06,2025-05-15_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 malwarescore=0 spamscore=0 lowpriorityscore=0 clxscore=1015 impostorscore=0 mlxlogscore=546 mlxscore=0 adultscore=0 bulkscore=0 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505150155 Received-SPF: pass client-ip=148.163.156.1; envelope-from=milesg@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: milesg@linux.ibm.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Reviewed-by: Glenn Miles On Mon, 2025-05-12 at 13:10 +1000, Nicholas Piggin wrote: > xive_tctx_pipr_present() as implemented with xive_tctx_pipr_update() > causes VP-directed (group==0) interrupt to be presented in PIPR and NSR > despite being a lower priority than the currently presented group > interrupt. > > This must not happen. The IPB bit should record the low priority VP > interrupt, but PIPR and NSR must not present the lower priority > interrupt. > > Signed-off-by: Nicholas Piggin > --- > hw/intc/xive.c | 18 +++++++++++++++++- > 1 file changed, 17 insertions(+), 1 deletion(-) > > diff --git a/hw/intc/xive.c b/hw/intc/xive.c > index bf4c0634ca..25f6c69c44 100644 > --- a/hw/intc/xive.c > +++ b/hw/intc/xive.c > @@ -228,7 +228,23 @@ void xive_tctx_pipr_update(XiveTCTX *tctx, uint8_t ring, uint8_t priority, > void xive_tctx_pipr_present(XiveTCTX *tctx, uint8_t ring, uint8_t priority, > uint8_t group_level) > { > - xive_tctx_pipr_update(tctx, ring, priority, group_level); > + /* HV_POOL ring uses HV_PHYS NSR, CPPR and PIPR registers */ > + uint8_t alt_ring = (ring == TM_QW2_HV_POOL) ? TM_QW3_HV_PHYS : ring; > + uint8_t *aregs = &tctx->regs[alt_ring]; > + uint8_t *regs = &tctx->regs[ring]; > + uint8_t pipr = xive_priority_to_pipr(priority); > + > + if (group_level == 0) { > + regs[TM_IPB] |= xive_priority_to_ipb(priority); > + if (pipr >= aregs[TM_PIPR]) { > + /* VP interrupts can come here with lower priority than PIPR */ > + return; > + } > + } > + g_assert(pipr <= xive_ipb_to_pipr(regs[TM_IPB])); > + g_assert(pipr < aregs[TM_PIPR]); > + aregs[TM_PIPR] = pipr; > + xive_tctx_notify(tctx, ring, group_level); > } > > /*