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[50.78.183.178]) by smtp.gmail.com with ESMTPSA id d5sm344942pfd.115.2021.05.29.18.09.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 29 May 2021 18:09:13 -0700 (PDT) Subject: Re: [PATCH] docs/devel: Explain in more detail the TB chaining mechanisms To: Luis Fernando Fujita Pires , "qemu-devel@nongnu.org" References: <20210528123029.143847-1-luis.pires@eldorado.org.br> <5690d0be-1e3b-a9f7-060a-8d08d9cd6c35@linaro.org> From: Richard Henderson Message-ID: <9ca93ebf-ab19-88d9-1b29-1ec73384cbbc@linaro.org> Date: Sat, 29 May 2021 18:09:09 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.8.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "pbonzini@redhat.com" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 5/28/21 1:15 PM, Luis Fernando Fujita Pires wrote: > From: Richard Henderson >> More completely, update the CPU state with any information that has been >> assumed constant. For most guests, this is just the PC. But e.g. for hppa >> this is both iaoq.f (cip) and iaoq.b (nip). >> >> It is very much up to the guest to determine the set of data that is present in >> cpu_get_tb_cpu_state, and what can be assumed across the break. > > I’m not sure I understand what “assumed constant” means in this context. The pc of the branch destination is a constant, for instance. As would be the enabled instruction set (consider arm's blx, which toggles between arm and thumb isa). > Would > it be fair to say that step 2 should update any CPU state information that is > required by the main loop to correctly locate and execute the next TB, but not > anything that would be needed if we were to jump directly from step 1 to the first > instruction in the next TB without going through the main loop? The information written in step 2, omitted by step 1, must be inferable from cpu_get_tb_cpu_state (via tcg_ops->synchronize_from_tb) and from cpu_restore_state. One of the two forms is how we return to the main loop after escaping from the chain of TB via interrupt or exception, respectively. r~