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[37.14.164.149]) by smtp.gmail.com with ESMTPSA id r83sm19905101wma.22.2021.11.29.06.34.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 29 Nov 2021 06:34:54 -0800 (PST) Subject: Re: [PATCH v3 2/8] accel/tcg: suppress IRQ check for special TBs To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-devel@nongnu.org References: <20211129140932.4115115-1-alex.bennee@linaro.org> <20211129140932.4115115-3-alex.bennee@linaro.org> From: Richard Henderson Message-ID: <9cb5c50d-114d-d515-c60f-17d3ccfe66ab@linaro.org> Date: Mon, 29 Nov 2021 15:34:51 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 MIME-Version: 1.0 In-Reply-To: <20211129140932.4115115-3-alex.bennee@linaro.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::42e (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.317, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: fam@euphon.net, berrange@redhat.com, David Hildenbrand , f4bug@amsat.org, Peter Xu , stefanha@redhat.com, crosa@redhat.com, pbonzini@redhat.com, Pavel Dovgalyuk , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , aurelien@aurel32.net Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 11/29/21 3:09 PM, Alex Bennée wrote: > When we set cpu->cflags_next_tb it is because we want to carefully > control the execution of the next TB. Currently there is a race that > causes the second stage of watchpoint handling to get ignored if an > IRQ is processed before we finish executing the instruction that > triggers the watchpoint. Use the new CF_NOIRQ facility to avoid the > race. > > We also suppress IRQs when handling precise self modifying code to > avoid unnecessary bouncing. > > Signed-off-by: Alex Bennée > Cc: Pavel Dovgalyuk > Fixes:https://gitlab.com/qemu-project/qemu/-/issues/245 > > --- > v2 > - split the CF_NOIRQ implementation > - only apply CF_NOIRQ for watchpoints/SMC handling > - minor reword of commit > v3 > - add additional two cases of | CF_NOIRQ > --- > accel/tcg/cpu-exec.c | 9 +++++++++ > accel/tcg/translate-all.c | 4 ++-- > softmmu/physmem.c | 4 ++-- > 3 files changed, 13 insertions(+), 4 deletions(-) Reviewed-by: Richard Henderson r~