From: Jiajie Chen <c@jia.je>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Cc: git@xen0n.name, gaosong@loongson.cn, yangxiaojuan@loongson.cn
Subject: Re: [PATCH 2/7] tcg/loongarch64: Use C_N2_I1 for INDEX_op_qemu_ld_a*_i128
Date: Sat, 30 Sep 2023 19:39:53 +0800 [thread overview]
Message-ID: <9cce79ee-ba15-4edb-859a-af3bd69b53bb@jia.je> (raw)
In-Reply-To: <20230916220151.526140-3-richard.henderson@linaro.org>
On 2023/9/17 06:01, Richard Henderson wrote:
> Use new registers for the output, so that we never overlap
> the input address, which could happen for user-only.
> This avoids a "tmp = addr + 0" in that case.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/loongarch64/tcg-target-con-set.h | 2 +-
> tcg/loongarch64/tcg-target.c.inc | 17 +++++++++++------
> 2 files changed, 12 insertions(+), 7 deletions(-)
>
> diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-target-con-set.h
> index 77d62e38e7..cae6c2aad6 100644
> --- a/tcg/loongarch64/tcg-target-con-set.h
> +++ b/tcg/loongarch64/tcg-target-con-set.h
> @@ -38,4 +38,4 @@ C_O1_I2(w, w, wM)
> C_O1_I2(w, w, wA)
> C_O1_I3(w, w, w, w)
> C_O1_I4(r, rZ, rJ, rZ, rZ)
> -C_O2_I1(r, r, r)
> +C_N2_I1(r, r, r)
> diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
> index b701df50db..40074c46b8 100644
> --- a/tcg/loongarch64/tcg-target.c.inc
> +++ b/tcg/loongarch64/tcg-target.c.inc
> @@ -1105,13 +1105,18 @@ static void tcg_out_qemu_ldst_i128(TCGContext *s, TCGReg data_lo, TCGReg data_hi
> }
> } else {
> /* Otherwise use a pair of LD/ST. */
> - tcg_out_opc_add_d(s, TCG_REG_TMP0, h.base, h.index);
> + TCGReg base = h.base;
> + if (h.index != TCG_REG_ZERO) {
> + base = TCG_REG_TMP0;
> + tcg_out_opc_add_d(s, base, h.base, h.index);
> + }
> if (is_ld) {
> - tcg_out_opc_ld_d(s, data_lo, TCG_REG_TMP0, 0);
> - tcg_out_opc_ld_d(s, data_hi, TCG_REG_TMP0, 8);
> + tcg_debug_assert(base != data_lo);
> + tcg_out_opc_ld_d(s, data_lo, base, 0);
> + tcg_out_opc_ld_d(s, data_hi, base, 8);
> } else {
> - tcg_out_opc_st_d(s, data_lo, TCG_REG_TMP0, 0);
> - tcg_out_opc_st_d(s, data_hi, TCG_REG_TMP0, 8);
> + tcg_out_opc_st_d(s, data_lo, base, 0);
> + tcg_out_opc_st_d(s, data_hi, base, 8);
> }
> }
>
> @@ -2049,7 +2054,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
>
> case INDEX_op_qemu_ld_a32_i128:
> case INDEX_op_qemu_ld_a64_i128:
> - return C_O2_I1(r, r, r);
> + return C_N2_I1(r, r, r);
>
> case INDEX_op_qemu_st_a32_i128:
> case INDEX_op_qemu_st_a64_i128:
Reviewed-by: Jiajie Chen <c@jia.je>
next prev parent reply other threads:[~2023-09-30 11:40 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-16 22:01 [PATCH 0/7] tcg/loongarch64: Improvements for 128-bit load/store Richard Henderson
2023-09-16 22:01 ` [PATCH 1/7] tcg: Add C_N2_I1 Richard Henderson
2023-09-30 11:39 ` Jiajie Chen
2023-09-16 22:01 ` [PATCH 2/7] tcg/loongarch64: Use C_N2_I1 for INDEX_op_qemu_ld_a*_i128 Richard Henderson
2023-09-30 11:39 ` Jiajie Chen [this message]
2023-09-16 22:01 ` [PATCH 3/7] util: Add cpuinfo for loongarch64 Richard Henderson
2023-09-30 11:40 ` Jiajie Chen
2023-09-16 22:01 ` [PATCH 4/7] tcg/loongarch64: Use cpuinfo.h Richard Henderson
2023-09-30 11:41 ` Jiajie Chen
2023-09-16 22:01 ` [PATCH 5/7] host/include/loongarch64: Add atomic16 load and store Richard Henderson
2023-09-16 22:01 ` [PATCH 6/7] accel/tcg: Remove redundant case in store_atom_16 Richard Henderson
2023-09-16 22:01 ` [PATCH 7/7] accel/tcg: Fix condition for store_atom_insert_al16 Richard Henderson
2023-09-30 2:13 ` [PATCH 0/7] tcg/loongarch64: Improvements for 128-bit load/store Richard Henderson
2023-09-30 19:04 ` WANG Xuerui
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