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Fri, 02 May 2025 11:12:05 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGzBds/R1iKGEWb4Vz1XzGA1IIdodCP9L87BaOdHn/rSUNRYqm05cXbAN207va439v4UPK8RQ== X-Received: by 2002:ac8:7f45:0:b0:476:884e:52f4 with SMTP id d75a77b69052e-48d5bf6e0a4mr1224881cf.12.1746209524632; Fri, 02 May 2025 11:12:04 -0700 (PDT) Received: from [192.168.40.164] ([70.105.235.240]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-48b98c1a459sm20940611cf.69.2025.05.02.11.12.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 02 May 2025 11:12:04 -0700 (PDT) Message-ID: <9cdb3f09-0925-4e10-b607-8fe1028b2ce0@redhat.com> Date: Fri, 2 May 2025 14:11:32 -0400 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 0/6] Add support for user creatable SMMUv3 device Content-Language: en-US To: Shameer Kolothum , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: eric.auger@redhat.com, peter.maydell@linaro.org, jgg@nvidia.com, nicolinc@nvidia.com, berrange@redhat.com, nathanc@nvidia.com, mochs@nvidia.com, smostafa@google.com, linuxarm@huawei.com, wangzhou1@hisilicon.com, jiangkunkun@huawei.com, jonathan.cameron@huawei.com, zhangfei.gao@linaro.org References: <20250502102707.110516-1-shameerali.kolothum.thodi@huawei.com> From: Donald Dutile In-Reply-To: <20250502102707.110516-1-shameerali.kolothum.thodi@huawei.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=ddutile@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.644, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 5/2/25 6:27 AM, Shameer Kolothum wrote: > Hi All, > > Changes from v1: > https://lore.kernel.org/qemu-devel/20250415081104.71708-1-shameerali.kolothum.thodi@huawei.com/ > > Addressed feedback on v1. Thanks to all. > 1. Retained the same name as the legacy SMMUv3(arm-smmuv3) for new > device type as well (instead of arm-smmuv3-dev type usage in v1). > 2. Changes to ACPI IORT to use the same struct SMMUv3Device for both > legacy SMMUv3 and the new SMMUV3 device > 3. Removed the restriction of creating SMMUv3 dev if virt ver > 9.2. > > Cover letter from v1: > > This patch series introduces support for a user-creatable SMMUv3 device > (-device arm-smmuv3) in QEMU. > > The implementation is based on feedback received from the RFCv2[0]: > "hw/arm/virt: Add support for user-creatable accelerated SMMUv3" > > Currently, QEMU's SMMUv3 emulation (iommu=smmuv3) is tied to the machine should it be clarified as 'to the machine's sysbus' ? > and does not support instantiating multiple SMMUv3 devices—each associated > with a separate PCIe root complex. In contrast, real-world ARM systems > often include multiple SMMUv3 instances, each bound to a different PCIe > root complex. > > This also lays the groundwork for supporting accelerated SMMUv3, as > proposed in the aforementioned RFC. Please note, the accelerated SMMUv3 > support is not part of this series and will be sent out as a separate > series later on top of this one. > > Summary of changes: > > -Introduces support for multiple -device arm-smmuv3-dev,bus=pcie.x Drop, as you've done elsewhere.........................^^^^ > instances. > > Example usage: > > -device arm-smmuv3,bus=pcie.0 > -device virtio-net-pci,bus=pcie.0 > -device pxb-pcie,id=pcie.1,bus_nr=2 > -device arm-smmuv3,bus=pcie.1 > -device pcie-root-port,id=pcie.port1,bus=pcie.1 > -device virtio-net-pci,bus=pcie.port1 > > -Supports either the legacy iommu=smmuv3 option or the new > "-device arm-smmuv3" model.> > -Adds device tree bindings for the new SMMUv3 device on the arm/virt > machine only, and only for the default pcie.0 root complex. > (Note: pxb-pcie root complexes are currently not supported with the > device tree due to known limitations[1].) > > Please take a look and let me know your feedback. > > Thanks, > Shameer > [0]:https://lore.kernel.org/qemu-devel/20250311141045.66620-1-shameerali.kolothum.thodi@huawei.com/ > [1]:https://lore.kernel.org/qemu-devel/20230421165037.2506-1-Jonathan.Cameron@huawei.com/ > > Nicolin Chen (1): > hw/arm/virt: Add an SMMU_IO_LEN macro > > Shameer Kolothum (5): > hw/arm/smmuv3: Add support to associate a PCIe RC > hw/arm/virt-acpi-build: Update IORT for multiple smmuv3 devices > hw/arm/virt: Factor out common SMMUV3 dt bindings code > hw/arm/virt: Add support for smmuv3 device > hw/arm/smmuv3: Enable smmuv3 device creation > > hw/arm/smmuv3.c | 27 +++++++ > hw/arm/virt-acpi-build.c | 162 +++++++++++++++++++++++++++++++-------- > hw/arm/virt.c | 112 ++++++++++++++++++++------- > hw/core/sysbus-fdt.c | 3 + > include/hw/arm/virt.h | 1 + > 5 files changed, 244 insertions(+), 61 deletions(-) >