From: Richard Henderson <richard.henderson@linaro.org>
To: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>, qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com,
alistair.francis@wdc.com, dbarboza@ventanamicro.com,
liwei1518@gmail.com, bmeng.cn@gmail.com,
TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Subject: Re: [PATCH v3 08/14] tcg/riscv: Implement vector cmp ops
Date: Thu, 5 Sep 2024 00:12:28 -0700 [thread overview]
Message-ID: <9d40d3f4-731d-478f-81ba-1c380ef9d0ae@linaro.org> (raw)
In-Reply-To: <20240904142739.854-9-zhiwei_liu@linux.alibaba.com>
On 9/4/24 07:27, LIU Zhiwei wrote:
> @@ -2322,6 +2411,51 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
> riscv_set_vec_config_vl(s, type);
> tcg_out_opc_vi(s, OPC_VXOR_VI, a0, a1, -1, true);
> break;
> + case INDEX_op_cmpsel_vec:
> + TCGArg a3, a4;
> + int c3, c4;
> + TCGCond cond;
While I suppose this compiles, it's not great to have new variables added randomly within
a switch. At minimum, add { } around the block, but consider breaking out a separate
tcg_out_cmpsel function, akin to tcg_out_movcond et al.
> @@ -2332,10 +2466,27 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
> void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
> TCGArg a0, ...)
> {
> + va_list va;
> + TCGv_vec v0, v1;
> + TCGArg a2, a3;
> +
> + va_start(va, a0);
> + v0 = temp_tcgv_vec(arg_temp(a0));
> + v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
> + a2 = va_arg(va, TCGArg);
> +
> switch (opc) {
> + case INDEX_op_cmp_vec:
> + a3 = va_arg(va, TCGArg);
> + vec_gen_6(INDEX_op_cmpsel_vec, type, vece, tcgv_vec_arg(v0),
> + tcgv_vec_arg(v1), a2,
> + tcgv_i64_arg(tcg_constant_i64(-1)),
> + tcgv_i64_arg(tcg_constant_i64(0)), a3);
> + break;
> default:
> g_assert_not_reached();
> }
> + va_end(va);
> }
Better to use "TCGArg a0, a1". Converting through arg_tmp + temp_tcgv_vec to v0/v1 and
then undoing that with tcgv_vec_arg is confusing.
r~
next prev parent reply other threads:[~2024-09-05 7:13 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-04 14:27 [PATCH v3 00/14] Add support for vector LIU Zhiwei
2024-09-04 14:27 ` [PATCH v3 01/14] tcg/op-gvec: Fix iteration step in 32-bit operation LIU Zhiwei
2024-09-04 14:27 ` [PATCH v3 02/14] util: Add RISC-V vector extension probe in cpuinfo LIU Zhiwei
2024-09-05 3:34 ` Richard Henderson
2024-09-09 7:18 ` LIU Zhiwei
2024-09-09 15:45 ` Richard Henderson
2024-09-10 2:47 ` LIU Zhiwei
2024-09-04 14:27 ` [PATCH v3 03/14] tcg/riscv: Add basic support for vector LIU Zhiwei
2024-09-05 4:05 ` Richard Henderson
2024-09-10 2:49 ` LIU Zhiwei
2024-09-04 14:27 ` [PATCH v3 04/14] tcg/riscv: Add riscv vset{i}vli support LIU Zhiwei
2024-09-05 6:03 ` Richard Henderson
2024-09-10 2:46 ` LIU Zhiwei
2024-09-10 4:34 ` Richard Henderson
2024-09-10 7:03 ` LIU Zhiwei
2024-09-04 14:27 ` [PATCH v3 05/14] tcg/riscv: Implement vector load/store LIU Zhiwei
2024-09-05 6:39 ` Richard Henderson
2024-09-10 3:04 ` LIU Zhiwei
2024-09-04 14:27 ` [PATCH v3 06/14] tcg/riscv: Implement vector mov/dup{m/i} LIU Zhiwei
2024-09-05 6:56 ` Richard Henderson
2024-09-10 1:13 ` LIU Zhiwei
2024-09-04 14:27 ` [PATCH v3 07/14] tcg/riscv: Add support for basic vector opcodes LIU Zhiwei
2024-09-05 6:57 ` Richard Henderson
2024-09-04 14:27 ` [PATCH v3 08/14] tcg/riscv: Implement vector cmp ops LIU Zhiwei
2024-09-05 7:12 ` Richard Henderson [this message]
2024-09-10 1:17 ` LIU Zhiwei
2024-09-04 14:27 ` [PATCH v3 09/14] tcg/riscv: Implement vector neg ops LIU Zhiwei
2024-09-04 14:27 ` [PATCH v3 10/14] tcg/riscv: Implement vector sat/mul ops LIU Zhiwei
2024-09-04 14:27 ` [PATCH v3 11/14] tcg/riscv: Implement vector min/max ops LIU Zhiwei
2024-09-04 14:27 ` [PATCH v3 12/14] tcg/riscv: Implement vector shs/v ops LIU Zhiwei
2024-09-04 14:27 ` [PATCH v3 13/14] tcg/riscv: Implement vector roti/v/x shi ops LIU Zhiwei
2024-09-04 14:27 ` [PATCH v3 14/14] tcg/riscv: Enable native vector support for TCG host LIU Zhiwei
2024-09-05 23:46 ` [PATCH v3 00/14] Add support for vector Alistair Francis
2024-09-10 3:08 ` LIU Zhiwei
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