From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [PATCH v6 30/41] target/arm: Flush tlb for ASID changes in EL2&0 translation regime
Date: Tue, 4 Feb 2020 13:58:10 +0000 [thread overview]
Message-ID: <9d60a4f6-3eae-3f68-97cf-dd41650b482b@linaro.org> (raw)
In-Reply-To: <CAFEAcA8y2Zfd=qM+U0-tQB1GfC59FOy08Rx-a5AvSaqbvCnGag@mail.gmail.com>
On 2/3/20 11:49 AM, Peter Maydell wrote:
> On Mon, 3 Feb 2020 at 11:36, Peter Maydell <peter.maydell@linaro.org> wrote:
>> Since we don't flush TLBs when HCR_EL2.E2H changes, I'm wondering
>> about this sequence:
>>
>> * initially HCR_EL2.E2H == 1 and the E2&0 TLBs are populated
>> * HCR_EL2.E2H is set to 0
>> * TTBR1_EL2 is written with a different ASID from step 1,
>> but we don't flush the TLBs because HCR_EL2.E2H is 0
>> * HCR_EL2.E2H is set to 1
>> * guest will pick up wrong-ASID TLB entries from step 1
>>
>> Does the architecture require that the guest did some TLB
>> maintenance ops somewhere along the line to avoid this?
>> I haven't tried to look for them, but given the different
>> ASIDs I'm not sure it does...
>
> ...HCR_EL2.E2H documents that it "is permitted to be cached
> in a TLB", which means that the guest has to do *some*
> TLB maintenance ops if it changes it; unclear exactly which,
> though...
TLBI ALLE2 would seem to fit the bill after E2H change.
r~
next prev parent reply other threads:[~2020-02-04 13:59 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-01 19:28 [PATCH v6 00/41] target/arm: Implement ARMv8.1-VHE Richard Henderson
2020-02-01 19:28 ` [PATCH v6 01/41] target/arm: Define isar_feature_aa64_vh Richard Henderson
2020-02-01 19:28 ` [PATCH v6 02/41] target/arm: Enable HCR_E2H for VHE Richard Henderson
2020-02-01 19:28 ` [PATCH v6 03/41] target/arm: Add CONTEXTIDR_EL2 Richard Henderson
2020-02-01 19:28 ` [PATCH v6 04/41] target/arm: Add TTBR1_EL2 Richard Henderson
2020-02-01 19:28 ` [PATCH v6 05/41] target/arm: Update CNTVCT_EL0 for VHE Richard Henderson
2020-02-01 19:28 ` [PATCH v6 06/41] target/arm: Split out vae1_tlbmask Richard Henderson
2020-02-01 19:28 ` [PATCH v6 07/41] target/arm: Split out alle1_tlbmask Richard Henderson
2020-02-01 19:28 ` [PATCH v6 08/41] target/arm: Simplify tlb_force_broadcast alternatives Richard Henderson
2020-02-01 19:28 ` [PATCH v6 09/41] target/arm: Rename ARMMMUIdx*_S12NSE* to ARMMMUIdx*_E10_* Richard Henderson
2020-02-01 19:28 ` [PATCH v6 10/41] target/arm: Rename ARMMMUIdx_S2NS to ARMMMUIdx_Stage2 Richard Henderson
2020-02-01 19:28 ` [PATCH v6 11/41] target/arm: Rename ARMMMUIdx_S1NSE* to ARMMMUIdx_Stage1_E* Richard Henderson
2020-02-01 19:28 ` [PATCH v6 12/41] target/arm: Rename ARMMMUIdx_S1SE[01] to ARMMMUIdx_SE10_[01] Richard Henderson
2020-02-01 19:28 ` [PATCH v6 13/41] target/arm: Rename ARMMMUIdx*_S1E3 to ARMMMUIdx*_SE3 Richard Henderson
2020-02-01 19:28 ` [PATCH v6 14/41] target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2 Richard Henderson
2020-02-01 19:28 ` [PATCH v6 15/41] target/arm: Recover 4 bits from TBFLAGs Richard Henderson
2020-02-01 19:28 ` [PATCH v6 16/41] target/arm: Expand TBFLAG_ANY.MMUIDX to 4 bits Richard Henderson
2020-02-01 19:28 ` [PATCH v6 17/41] target/arm: Rearrange ARMMMUIdxBit Richard Henderson
2020-02-01 19:28 ` [PATCH v6 18/41] target/arm: Tidy ARMMMUIdx m-profile definitions Richard Henderson
2020-02-01 19:28 ` [PATCH v6 19/41] target/arm: Reorganize ARMMMUIdx Richard Henderson
2020-02-01 19:28 ` [PATCH v6 20/41] target/arm: Add regime_has_2_ranges Richard Henderson
2020-02-01 19:28 ` [PATCH v6 21/41] target/arm: Update arm_mmu_idx for VHE Richard Henderson
2020-02-01 19:28 ` [PATCH v6 22/41] target/arm: Update arm_sctlr " Richard Henderson
2020-02-01 19:28 ` [PATCH v6 23/41] target/arm: Update aa64_zva_access for EL2 Richard Henderson
2020-02-01 19:28 ` [PATCH v6 24/41] target/arm: Update ctr_el0_access " Richard Henderson
2020-02-01 19:29 ` [PATCH v6 25/41] target/arm: Add the hypervisor virtual counter Richard Henderson
2020-02-01 19:29 ` [PATCH v6 26/41] target/arm: Update timer access for VHE Richard Henderson
2020-02-01 19:29 ` [PATCH v6 27/41] target/arm: Update define_one_arm_cp_reg_with_opaque " Richard Henderson
2020-02-01 19:29 ` [PATCH v6 28/41] target/arm: Add VHE system register redirection and aliasing Richard Henderson
2020-02-01 19:29 ` [PATCH v6 29/41] target/arm: Add VHE timer " Richard Henderson
2020-02-01 19:29 ` [PATCH v6 30/41] target/arm: Flush tlb for ASID changes in EL2&0 translation regime Richard Henderson
2020-02-03 11:36 ` Peter Maydell
2020-02-03 11:49 ` Peter Maydell
2020-02-04 13:58 ` Richard Henderson [this message]
2020-02-01 19:29 ` [PATCH v6 31/41] target/arm: Flush tlbs for E2&0 " Richard Henderson
2020-02-03 11:30 ` Peter Maydell
2020-02-01 19:29 ` [PATCH v6 32/41] target/arm: Update arm_phys_excp_target_el for TGE Richard Henderson
2020-02-01 19:29 ` [PATCH v6 33/41] target/arm: Update {fp,sve}_exception_el for VHE Richard Henderson
2020-02-01 19:29 ` [PATCH v6 34/41] target/arm: check TGE and E2H flags for EL0 pauth traps Richard Henderson
2020-02-01 19:29 ` [PATCH v6 35/41] target/arm: Update get_a64_user_mem_index for VHE Richard Henderson
2020-02-01 19:29 ` [PATCH v6 36/41] target/arm: Update arm_cpu_do_interrupt_aarch64 " Richard Henderson
2020-02-01 19:29 ` [PATCH v6 37/41] target/arm: Enable ARMv8.1-VHE in -cpu max Richard Henderson
2020-02-01 19:29 ` [PATCH v6 38/41] target/arm: Move arm_excp_unmasked to cpu.c Richard Henderson
2020-02-01 19:29 ` [PATCH v6 39/41] target/arm: Pass more cpu state to arm_excp_unmasked Richard Henderson
2020-02-01 19:29 ` [PATCH v6 40/41] target/arm: Use bool for unmasked in arm_excp_unmasked Richard Henderson
2020-02-01 19:29 ` [PATCH v6 41/41] target/arm: Raise only one interrupt in arm_cpu_exec_interrupt Richard Henderson
2020-02-03 17:51 ` [PATCH v6 00/41] target/arm: Implement ARMv8.1-VHE Alex Bennée
2020-02-04 14:08 ` Richard Henderson
2020-02-06 10:44 ` Alex Bennée
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