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Tue, 06 Aug 2024 00:32:38 -0700 (PDT) Message-ID: <9da48ab0-d88e-4d80-aca6-79dfa083bb9b@linaro.org> Date: Tue, 6 Aug 2024 17:29:21 +1000 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/2] include: bitops: Add mask extract64/deposit64 To: Alistair Francis , qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: dbarboza@ventanamicro.com, Palmer Dabbelt , Weiwei Li , zhiwei_liu@linux.alibaba.com, Alistair Francis , atishp@rivosinc.com, bmeng.cn@gmail.com, qemu-riscv@nongnu.org References: <20240805043336.72548-1-alistair.francis@wdc.com> <20240805043336.72548-2-alistair.francis@wdc.com> Content-Language: en-US From: Richard Henderson In-Reply-To: <20240805043336.72548-2-alistair.francis@wdc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 8/5/24 14:33, Alistair Francis wrote: > Based on the RISC-V get_field() and set_field() macros add > mask_extract64() and mask_deposit64() bitop functions. These can extrac > and deposit values into fields using a bit field mask directly instead > of a length and shift. > > Signed-off-by: Alistair Francis > --- > include/qemu/bitops.h | 35 +++++++++++++++++++++++++++++++++++ > 1 file changed, 35 insertions(+) > > diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h > index 2c0a2fe751..dd26f4a6b5 100644 > --- a/include/qemu/bitops.h > +++ b/include/qemu/bitops.h > @@ -409,6 +409,22 @@ static inline uint64_t extract64(uint64_t value, int start, int length) > return (value >> start) & (~0ULL >> (64 - length)); > } > > +/** > + * mask_extract64: > + * @value: the value to extract the bit field from > + * @mask: the mask bit field to extract > + * > + * Extract from the 64 bit input @value the bit mask specified by the > + * @mask parameter, and return it. The value returned is shifted > + * so that only the bit field is returned. > + * > + * Returns: the value of the bit field extracted from the input value. > + */ > +static inline uint64_t mask_extract64(uint64_t value, uint64_t mask) > +{ > + return (value & mask) / (mask & ~(mask << 1)); > +} Adding these miss the point of using "standard" qemu operations. But if we were going to add this, avoid the division. (value & mask) >> ctz64(mask) I presume the original formulation is so that the macro can be used in the context of a compile-time constant. r~