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([2a01:e0a:9e2:9000:d55d:ba01:adf2:d3ae]) by smtp.gmail.com with ESMTPSA id qj22-20020a056214321600b0068cc0b46682sm414273qvb.4.2024.02.19.10.26.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 19 Feb 2024 10:26:28 -0800 (PST) Message-ID: <9db64273-d7e6-445c-bfe4-dcf7d90ee892@redhat.com> Date: Mon, 19 Feb 2024 19:26:24 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: Trying to write data to i2c bus Content-Language: en-US, fr To: minyard@acm.org, Paz Offer Cc: "qemu-devel@nongnu.org" References: From: =?UTF-8?Q?C=C3=A9dric_Le_Goater?= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=clegoate@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.072, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_SORBS_WEB=1.5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2/19/24 18:14, Corey Minyard wrote: > On Mon, Feb 19, 2024 at 04:53:47PM +0000, Paz Offer wrote: >> Thank you very much Corey, >> >> I am simulating an external module that wants to communicate with the board management controller (BMC). >> The real device will be connected to the board using i2c bus, and could initiate communication at any time, by sending bytes over the bus. > > And you have a simulated BMC that can do this? Or is the system running > in qemu the BMC. > >> >> I am not sure whether the 'Master-side' (the side the initiating communication) needs to simulate a full i2c-master device, or whether my code could 'simply' write directly to the appropriate registers of the guest OS. >> Are there some examples or documentation on how to implement something like this? > > The aspeed i2c controller is capable of having another bus master on an > I2C but, but it is the only host that can currently do it. > > It is doable, the code is ther for multiple bus masters, but there is no > device currently that does it. I assume that is coming at some point, > but no documentation exists on how to do it. > > You can look at the git commits in hw/i2c around 37fa5ca42623 "hw/i2c: > support multiple masters" for the changes that were done to support > this. There is an i2c-echo device implementing an I2C slave and a test, test_arm_ast2600_evb_buildroot in tests/avocado/ machine_aspeed.py, using it on the ast2600-evb. Thanks, C.