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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id jj13-20020a170903048d00b001967692d6f5sm5078973plb.227.2023.02.27.15.08.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 27 Feb 2023 15:08:14 -0800 (PST) Message-ID: <9e05f3ff-07f1-50f4-3069-0161a5c54404@linaro.org> Date: Mon, 27 Feb 2023 13:08:11 -1000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.1 Subject: Re: [PATCH v3 17/27] target/riscv: Replace `tb_pc()` with `tb->pc` Content-Language: en-US To: Palmer Dabbelt , anjo@rev.ng Cc: qemu-devel References: From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.089, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2/27/23 13:05, Palmer Dabbelt wrote: > On Mon, 27 Feb 2023 05:51:52 PST (-0800), anjo@rev.ng wrote: >> Signed-off-by: Anton Johansson >> Reviewed-by: Philippe Mathieu-Daudé >> --- >>  target/riscv/cpu.c | 7 +++++-- >>  1 file changed, 5 insertions(+), 2 deletions(-) >> >> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c >> index 93b52b826c..9eb748a283 100644 >> --- a/target/riscv/cpu.c >> +++ b/target/riscv/cpu.c >> @@ -34,6 +34,7 @@ >>  #include "fpu/softfloat-helpers.h" >>  #include "sysemu/kvm.h" >>  #include "kvm_riscv.h" >> +#include "tcg/tcg.h" >> >>  /* RISC-V CPU definitions */ >> >> @@ -533,10 +534,12 @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs, >>      CPURISCVState *env = &cpu->env; >>      RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); >> >> +    tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); >> + >>      if (xl == MXL_RV32) { >> -        env->pc = (int32_t)tb_pc(tb); >> +        env->pc = (int32_t) tb->pc; >>      } else { >> -        env->pc = tb_pc(tb); >> +        env->pc = tb->pc; >>      } >>  } > > Reviewed-by: Palmer Dabbelt > Acked-by: Palmer Dabbelt > > Thanks!  I'm going to assume you want these to stay together, but LMK if you were looking > to aim this at the RISC-V tree. I've queued to tcg-next, so they'll stay together. I've now added your r-b. r~