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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id z1sm3522424pfr.88.2020.06.11.09.09.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 11 Jun 2020 09:09:13 -0700 (PDT) Subject: Re: [PATCH 03/10] target/arm: Convert Neon 2-reg-scalar integer multiplies to decodetree To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20200611144529.8873-1-peter.maydell@linaro.org> <20200611144529.8873-4-peter.maydell@linaro.org> From: Richard Henderson Message-ID: <9e1c9363-2c6e-dd3b-3e2c-c28b9bd42c54@linaro.org> Date: Thu, 11 Jun 2020 09:09:11 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 MIME-Version: 1.0 In-Reply-To: <20200611144529.8873-4-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::642; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x642.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 6/11/20 7:45 AM, Peter Maydell wrote: > Convert the VMLA, VMLS and VMUL insns in the Neon "2 registers and a > scalar" group to decodetree. These are 32x32->32 operations where > one of the inputs is the scalar, followed by a possible accumulate > operation of the 32-bit result. > > The refactoring removes some of the oddities of the old decoder: > * operands to the operation and accumulation were often > reversed (taking advantage of the fact that most of these ops > are commutative); the new code follows the pseudocode order > * the Q bit in the insn was in a local variable 'u'; in the > new code it is decoded into a->q > > Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson > +static void gen_neon_dup_low16(TCGv_i32 var) > +{ > + TCGv_i32 tmp = tcg_temp_new_i32(); > + tcg_gen_ext16u_i32(var, var); > + tcg_gen_shli_i32(tmp, var, 16); > + tcg_gen_or_i32(var, var, tmp); > + tcg_temp_free_i32(tmp); > +} > + > +static void gen_neon_dup_high16(TCGv_i32 var) > +{ > + TCGv_i32 tmp = tcg_temp_new_i32(); > + tcg_gen_andi_i32(var, var, 0xffff0000); > + tcg_gen_shri_i32(tmp, var, 16); > + tcg_gen_or_i32(var, var, tmp); > + tcg_temp_free_i32(tmp); > +} I was going to quibble about this implementation, but see that it's a straight move from translate.c. The real TODO should be a conversion to tcg_gen_gvec_2s(), so that we use real vector multiplies and adds here, with the scalar duped across the vector, not just an i32. r~