From: Andrzej Jakowski <andrzej.jakowski@linux.intel.com>
To: "Klaus Jensen" <its@irrelevant.dk>,
"Philippe Mathieu-Daudé" <philmd@redhat.com>
Cc: Kevin Wolf <kwolf@redhat.com>,
qemu-block@nongnu.org, Klaus Jensen <k.jensen@samsung.com>,
qemu-devel@nongnu.org, Max Reitz <mreitz@redhat.com>,
Keith Busch <kbusch@kernel.org>
Subject: Re: [PATCH v3 3/4] hw/block/nvme: Fix pmrmsc register size
Date: Wed, 1 Jul 2020 16:08:54 -0700 [thread overview]
Message-ID: <9e3b7248-785a-72f0-b99b-af91740f1df7@linux.intel.com> (raw)
In-Reply-To: <20200630164541.tnnabrqzejaumwrr@apples.localdomain>
On 6/30/20 9:45 AM, Klaus Jensen wrote:
> On Jun 30 17:16, Philippe Mathieu-Daudé wrote:
>> On 6/30/20 5:10 PM, Andrzej Jakowski wrote:
>>> On 6/30/20 4:04 AM, Philippe Mathieu-Daudé wrote:
>>>> The Persistent Memory Region Controller Memory Space Control
>>>> register is 64-bit wide. See 'Figure 68: Register Definition'
>>>> of the 'NVM Express Base Specification Revision 1.4'.
>>>>
>>>> Fixes: 6cf9413229 ("introduce PMR support from NVMe 1.4 spec")
>>>> Reported-by: Klaus Jensen <k.jensen@samsung.com>
>>>> Reviewed-by: Klaus Jensen <k.jensen@samsung.com>
>>>> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>>>> ---
>>>> Cc: Andrzej Jakowski <andrzej.jakowski@linux.intel.com>
>>>> ---
>>>> include/block/nvme.h | 2 +-
>>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>>
>>>> diff --git a/include/block/nvme.h b/include/block/nvme.h
>>>> index 71c5681912..82c384614a 100644
>>>> --- a/include/block/nvme.h
>>>> +++ b/include/block/nvme.h
>>>> @@ -21,7 +21,7 @@ typedef struct QEMU_PACKED NvmeBar {
>>>> uint32_t pmrsts;
>>>> uint32_t pmrebs;
>>>> uint32_t pmrswtp;
>>>> - uint32_t pmrmsc;
>>>> + uint64_t pmrmsc;
>>>> } NvmeBar;
>>>>
>>>> enum NvmeCapShift {
>>>> -- 2.21.3
>>>
>>> This is good catch, though I wanted to highlight that this will still
>>> need to change as this register is not aligned properly and thus not in
>>> compliance with spec.
>>
>> I was wondering the odd alignment too. So you are saying at some time
>> in the future the spec will be updated to correct the alignment?
Yep I think so.
So PMRMSC currently is 64-bit register that is defined at E14h offset.
It is in conflict with spec because spec requires 64-bit registers to
be 64-bit aligned.
I anticipate that changes will be needed.
>>
>> Should we use this instead?
>>
>> uint32_t pmrmsc;
>> + uint32_t pmrmsc_upper32; /* the spec define this, but *
>> + * only low 32-bit are used */
>>
>> Or eventually an unnamed struct:
>>
>> - uint32_t pmrmsc;
>> + struct {
>> + uint32_t pmrmsc;
>> + uint32_t pmrmsc_upper32; /* the spec define this, but *
>> + * only low 32-bit are used */
>> + };
>>
>>>
>>> Reviewed-by Andrzej Jakowski <andrzej.jakowski@linux.intel.com>
>>>
>>
>
> I'm also not sure what you mean Andrzej. The odd alignment is exactly
> what the spec (v1.4) says?
>
next prev parent reply other threads:[~2020-07-01 23:09 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-30 11:04 [PATCH v3 0/4] hw/block/nvme: Fix I/O BAR structure Philippe Mathieu-Daudé
2020-06-30 11:04 ` [PATCH v3 1/4] hw/block/nvme: Update specification URL Philippe Mathieu-Daudé
2020-07-08 22:11 ` Dmitry Fomichev
2020-06-30 11:04 ` [PATCH v3 2/4] hw/block/nvme: Use QEMU_PACKED on hardware/packet structures Philippe Mathieu-Daudé
2020-07-13 0:56 ` Dmitry Fomichev
2020-06-30 11:04 ` [PATCH v3 3/4] hw/block/nvme: Fix pmrmsc register size Philippe Mathieu-Daudé
2020-06-30 15:10 ` Andrzej Jakowski
2020-06-30 15:16 ` Philippe Mathieu-Daudé
2020-06-30 16:45 ` Klaus Jensen
2020-07-01 23:08 ` Andrzej Jakowski [this message]
2020-07-13 1:07 ` Dmitry Fomichev
2020-06-30 11:04 ` [PATCH v3 4/4] hw/block/nvme: Align I/O BAR to 4 KiB Philippe Mathieu-Daudé
2020-07-13 1:07 ` Dmitry Fomichev
2020-07-13 7:51 ` [PATCH v3 0/4] hw/block/nvme: Fix I/O BAR structure Klaus Jensen
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=9e3b7248-785a-72f0-b99b-af91740f1df7@linux.intel.com \
--to=andrzej.jakowski@linux.intel.com \
--cc=its@irrelevant.dk \
--cc=k.jensen@samsung.com \
--cc=kbusch@kernel.org \
--cc=kwolf@redhat.com \
--cc=mreitz@redhat.com \
--cc=philmd@redhat.com \
--cc=qemu-block@nongnu.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).