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From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= <philmd@redhat.com>
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Date: Mon, 18 Feb 2019 22:43:05 +0100
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Subject: Re: [Qemu-devel] [PATCH 1/7] hw/misc: mips_itu: Fix 32/64 bit issue
 in a line involving shift operator
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To: Aleksandar Markovic <aleksandar.markovic@rt-rk.com>, qemu-devel@nongnu.org
Cc: arikalo@wavecomp.com, peter.maydell@linaro.org, amarkovic@wavecomp.com, aurelien@aurel32.net

On 2/18/19 4:31 PM, Aleksandar Markovic wrote:
> From: Aleksandar Markovic <amarkovic@wavecomp.com>
> 
> Fix 32/64 bit issue in a line involving shift operator. "1 << ..."
> calculation of size is done as a 32-bit signed integer which may
> then be unintentionally sign-extended into the 64-bit result. The
> problem was discovered by Coverity (CID 1398648). Using "1ULL"
> instead of "1" on the LHS of the shift fixes this problem.
> 
> Reproted-by: Peter Maydell <peter.maydell@linaro.org>

Reported-by

> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>

> ---
>  hw/misc/mips_itu.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c
> index 1257d8f..3afdbe6 100644
> --- a/hw/misc/mips_itu.c
> +++ b/hw/misc/mips_itu.c
> @@ -94,7 +94,7 @@ void itc_reconfigure(MIPSITUState *tag)
>  
>      if (tag->saar_present) {
>          address = ((*(uint64_t *) tag->saar) & 0xFFFFFFFFE000ULL) << 4;
> -        size = 1 << ((*(uint64_t *) tag->saar >> 1) & 0x1f);
> +        size = 1ULL << ((*(uint64_t *) tag->saar >> 1) & 0x1f);
>          is_enabled = *(uint64_t *) tag->saar & 1;
>      }
>  
>