Re: [Qemu-devel] [PATCH v3b 18/18] target/arm: Implement SVE Floating Point Arithmetic - Unpredicated Group

[Richard Henderson <richard.henderson@linaro.org>]

On 06/07/2018 03:45 AM, Peter Maydell wrote:
> On 30 May 2018 at 19:01, Richard Henderson <richard.henderson@linaro.org> wrote:
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>>  target/arm/helper-sve.h    | 14 ++++++++
>>  target/arm/helper.h        | 19 +++++++++++
>>  target/arm/translate-sve.c | 42 +++++++++++++++++++++++
>>  target/arm/vec_helper.c    | 69 ++++++++++++++++++++++++++++++++++++++
>>  target/arm/sve.decode      | 10 ++++++
>>  5 files changed, 154 insertions(+)
>>
> 
>> +DO_3OP(gvec_fadd_h, float16_add, float16)
>> +DO_3OP(gvec_fadd_s, float32_add, float32)
>> +DO_3OP(gvec_fadd_d, float64_add, float64)
>> +
>> +DO_3OP(gvec_fsub_h, float16_sub, float16)
>> +DO_3OP(gvec_fsub_s, float32_sub, float32)
>> +DO_3OP(gvec_fsub_d, float64_sub, float64)
>> +
>> +DO_3OP(gvec_fmul_h, float16_mul, float16)
>> +DO_3OP(gvec_fmul_s, float32_mul, float32)
>> +DO_3OP(gvec_fmul_d, float64_mul, float64)
>> +
>> +DO_3OP(gvec_ftsmul_h, float16_ftsmul, float16)
>> +DO_3OP(gvec_ftsmul_s, float32_ftsmul, float32)
>> +DO_3OP(gvec_ftsmul_d, float64_ftsmul, float64)
>> +
>> +#ifdef TARGET_AARCH64
>> +
>> +DO_3OP(gvec_recps_h, helper_recpsf_f16, float16)
>> +DO_3OP(gvec_recps_s, helper_recpsf_f32, float32)
>> +DO_3OP(gvec_recps_d, helper_recpsf_f64, float64)
>> +
>> +DO_3OP(gvec_rsqrts_h, helper_rsqrtsf_f16, float16)
>> +DO_3OP(gvec_rsqrts_s, helper_rsqrtsf_f32, float32)
>> +DO_3OP(gvec_rsqrts_d, helper_rsqrtsf_f64, float64)
>> +
>> +#endif
>> +#undef DO_3OP
> 
> Why do only these ones need to be guarded by the TARGET_AARCH64 ifdef?

(1) The first ones can be used when re-implementing aa32 neon.  The last ones
are operations not present in aa32.  (2) The last ones are implemented using
helpers-a64.c.


r~