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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id y7sm8697823pgk.93.2020.06.25.09.54.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 25 Jun 2020 09:54:57 -0700 (PDT) Subject: Re: [PATCH v8 38/45] target/arm: Complete TBI clearing for user-only for SVE To: Peter Maydell References: <20200623193658.623279-1-richard.henderson@linaro.org> <20200623193658.623279-39-richard.henderson@linaro.org> From: Richard Henderson Message-ID: <9e80eb42-655f-9ffa-264a-f72627efdf42@linaro.org> Date: Thu, 25 Jun 2020 09:54:55 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::543; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x543.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: david.spickett@linaro.org, qemu-arm , QEMU Developers , Stephen Long Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 6/25/20 5:52 AM, Peter Maydell wrote: > On Tue, 23 Jun 2020 at 20:37, Richard Henderson > wrote: >> >> There are a number of paths by which the TBI is still intact >> for user-only in the SVE helpers. >> >> Because we currently always set TBI for user-only, we do not >> need to pass down the actual TBI setting from above, and we >> can remove the top byte in the inner-most primitives, so that >> none are forgotten. Moreover, this keeps the "dirty" pointer >> around at the higher levels, where we need it for any MTE checking. >> >> Since the normal case, especially for user-only, goes through >> RAM, this clearing merely adds two insns per page lookup, which >> will be completely in the noise. > > Can we have an assert() somewhere suitable that TBI is set? > That way if we ever do have an SVE-capable linux-user which > doesn't set TBI for some reason we'll get a useful reminder > that we need to fix something. At what level would you like such an assert? At present we have, in arm_cpu_reset, /* * Enable TBI0 and TBI1. While the real kernel only enables TBI0, * turning on both here will produce smaller code and otherwise * make no difference to the user-level emulation. */ env->cp15.tcr_el[1].raw_tcr = (3ULL << 37); r~