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([2a01:e0a:280:24f0:3f78:514a:4f03:fdc0]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6c162d21710sm48068266d6.11.2024.08.26.09.34.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 26 Aug 2024 09:34:46 -0700 (PDT) Message-ID: <9eef76cf-3e89-4d67-85b8-e32b5c2a4686@redhat.com> Date: Mon, 26 Aug 2024 18:34:44 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/7] ppc/pnv: Fix LPC serirq routing calculation To: Nicholas Piggin , qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org References: <20240806131318.275109-1-npiggin@gmail.com> <20240806131318.275109-2-npiggin@gmail.com> Content-Language: en-US, fr From: =?UTF-8?Q?C=C3=A9dric_Le_Goater?= In-Reply-To: <20240806131318.275109-2-npiggin@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 8/6/24 15:13, Nicholas Piggin wrote: > The serirq routing table is split over two registers, the calculation > for the high irqs in the second register did not subtract the irq > offset. This was spotted by Coverity as a shift-by-negative. Fix this > and change the open-coded shifting and masking to use extract32() > function so it's less error-prone. > > This went unnoticed because irqs >= 14 are not used in a standard > QEMU/OPAL boot, changing the first QEMU serial-isa irq to 14 to test > does demonstrate serial irqs aren't received, and that this change > fixes that. > > Reported-by: Cédric Le Goater > Resolves: Coverity CID 1558829 (partially) > Signed-off-by: Nicholas Piggin Reviewed-by: Cédric Le Goater Thanks, C. > --- > target/ppc/cpu.h | 1 + > hw/ppc/pnv_lpc.c | 10 ++++++++-- > 2 files changed, 9 insertions(+), 2 deletions(-) > > diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h > index 321ed2da75..bd32a1a5f8 100644 > --- a/target/ppc/cpu.h > +++ b/target/ppc/cpu.h > @@ -40,6 +40,7 @@ > > #define PPC_BIT_NR(bit) (63 - (bit)) > #define PPC_BIT(bit) (0x8000000000000000ULL >> (bit)) > +#define PPC_BIT32_NR(bit) (31 - (bit)) > #define PPC_BIT32(bit) (0x80000000 >> (bit)) > #define PPC_BIT8(bit) (0x80 >> (bit)) > #define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs)) > diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c > index f8aad955b5..80b79dfbbc 100644 > --- a/hw/ppc/pnv_lpc.c > +++ b/hw/ppc/pnv_lpc.c > @@ -435,13 +435,19 @@ static void pnv_lpc_eval_serirq_routes(PnvLpcController *lpc) > return; > } > > + /* > + * Each of the ISA irqs is routed to one of the 4 SERIRQ irqs with 2 > + * bits, split across 2 OPB registers. > + */ > for (irq = 0; irq <= 13; irq++) { > - int serirq = (lpc->opb_irq_route1 >> (31 - 5 - (irq * 2))) & 0x3; > + int serirq = extract32(lpc->opb_irq_route1, > + PPC_BIT32_NR(5 + irq * 2), 2); > lpc->irq_to_serirq_route[irq] = serirq; > } > > for (irq = 14; irq < ISA_NUM_IRQS; irq++) { > - int serirq = (lpc->opb_irq_route0 >> (31 - 9 - (irq * 2))) & 0x3; > + int serirq = extract32(lpc->opb_irq_route0, > + PPC_BIT32_NR(9 + (irq - 14) * 2), 2); > lpc->irq_to_serirq_route[irq] = serirq; > } > }