From: "Philippe Mathieu-Daudé" <philmd@redhat.com>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: Re: [PATCH 02/11] target/arm: Add arm_mmu_idx_is_stage1
Date: Wed, 4 Dec 2019 16:35:17 +0100 [thread overview]
Message-ID: <9f24817e-54dc-dbca-e3f9-09ed185d025f@redhat.com> (raw)
In-Reply-To: <20191203225333.17055-3-richard.henderson@linaro.org>
On 12/3/19 11:53 PM, Richard Henderson wrote:
> Use a common predicate for querying stage1-ness.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> target/arm/internals.h | 11 +++++++++++
> target/arm/helper.c | 8 +++-----
> 2 files changed, 14 insertions(+), 5 deletions(-)
>
> diff --git a/target/arm/internals.h b/target/arm/internals.h
> index 49dac2a677..850f204f14 100644
> --- a/target/arm/internals.h
> +++ b/target/arm/internals.h
> @@ -1034,6 +1034,17 @@ static inline ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env)
> ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env);
> #endif
>
> +static inline bool arm_mmu_idx_is_stage1(ARMMMUIdx mmu_idx)
> +{
> + switch (mmu_idx) {
> + case ARMMMUIdx_Stage1_E0:
> + case ARMMMUIdx_Stage1_E1:
> + return true;
> + default:
> + return false;
> + }
> +}
> +
> /*
> * Parameters of a given virtual address, as extracted from the
> * translation control register (TCR) for a given regime.
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index f3785d5ad6..fdb86ea427 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -3212,8 +3212,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
> bool take_exc = false;
>
> if (fi.s1ptw && current_el == 1 && !arm_is_secure(env)
> - && (mmu_idx == ARMMMUIdx_Stage1_E1
> - || mmu_idx == ARMMMUIdx_Stage1_E0)) {
> + && arm_mmu_idx_is_stage1(mmu_idx)) {
> /*
> * Synchronous stage 2 fault on an access made as part of the
> * translation table walk for AT S1E0* or AT S1E1* insn
> @@ -9159,8 +9158,7 @@ static inline bool regime_translation_disabled(CPUARMState *env,
> }
> }
>
> - if ((env->cp15.hcr_el2 & HCR_DC) &&
> - (mmu_idx == ARMMMUIdx_Stage1_E0 || mmu_idx == ARMMMUIdx_Stage1_E1)) {
> + if ((env->cp15.hcr_el2 & HCR_DC) && arm_mmu_idx_is_stage1(mmu_idx)) {
> /* HCR.DC means SCTLR_EL1.M behaves as 0 */
> return true;
> }
> @@ -9469,7 +9467,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
> hwaddr addr, MemTxAttrs txattrs,
> ARMMMUFaultInfo *fi)
> {
> - if ((mmu_idx == ARMMMUIdx_Stage1_E0 || mmu_idx == ARMMMUIdx_Stage1_E1) &&
> + if (arm_mmu_idx_is_stage1(mmu_idx) &&
> !regime_translation_disabled(env, ARMMMUIdx_Stage2)) {
> target_ulong s2size;
> hwaddr s2pa;
>
next prev parent reply other threads:[~2019-12-04 15:39 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-03 22:53 [PATCH 00/11] target/arm: Implement ARMv8.1-PAN + ARMv8.2-ATS1E1 Richard Henderson
2019-12-03 22:53 ` [PATCH 01/11] cputlb: Handle NB_MMU_MODES > TARGET_PAGE_BITS_MIN Richard Henderson
2019-12-06 18:56 ` Peter Maydell
2019-12-03 22:53 ` [PATCH 02/11] target/arm: Add arm_mmu_idx_is_stage1 Richard Henderson
2019-12-04 15:35 ` Philippe Mathieu-Daudé [this message]
2019-12-06 19:00 ` Peter Maydell
2019-12-03 22:53 ` [PATCH 03/11] target/arm: Add mmu_idx for EL1 and EL2 w/ PAN enabled Richard Henderson
2019-12-09 11:40 ` Peter Maydell
2019-12-03 22:53 ` [PATCH 04/11] target/arm: Reduce CPSR_RESERVED Richard Henderson
2019-12-06 19:06 ` Peter Maydell
2019-12-03 22:53 ` [PATCH 05/11] target/arm: Add isar_feature tests for PAN + ATS1E1 Richard Henderson
2019-12-06 19:07 ` Peter Maydell
2019-12-03 22:53 ` [PATCH 06/11] target/arm: Update MSR access for PAN Richard Henderson
2019-12-06 19:10 ` Peter Maydell
2019-12-03 22:53 ` [PATCH 07/11] target/arm: Update arm_mmu_idx_el " Richard Henderson
2019-12-06 19:10 ` Peter Maydell
2019-12-03 22:53 ` [PATCH 08/11] target/arm: Enforce PAN semantics in get_S1prot Richard Henderson
2019-12-06 19:12 ` Peter Maydell
2019-12-03 22:53 ` [PATCH 09/11] target/arm: Set PAN bit as required on exception entry Richard Henderson
2019-12-09 11:55 ` Peter Maydell
2019-12-03 22:53 ` [PATCH 10/11] target/arm: Implement ATS1E1 system registers Richard Henderson
2019-12-09 13:41 ` Peter Maydell
2020-01-31 21:38 ` Richard Henderson
2019-12-03 22:53 ` [PATCH 11/11] target/arm: Enable ARMv8.2-ATS1E1 in -cpu max Richard Henderson
2019-12-06 19:14 ` Peter Maydell
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