From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
To: Bin Meng <bmeng@tinylab.org>, qemu-devel@nongnu.org
Cc: Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Weiwei Li <liweiwei@iscas.ac.cn>,
qemu-riscv@nongnu.org
Subject: Re: [PATCH 05/18] target/riscv: Coding style fixes in csr.c
Date: Fri, 17 Feb 2023 10:24:13 +0800 [thread overview]
Message-ID: <9f30a217-d429-1ce1-e5de-3678af40e8e3@linux.alibaba.com> (raw)
In-Reply-To: <20230213180215.1524938-6-bmeng@tinylab.org>
On 2023/2/14 2:02, Bin Meng wrote:
> Fix various places that violate QEMU coding style:
>
> - correct multi-line comment format
> - indent to opening parenthesis
>
> Signed-off-by: Bin Meng <bmeng@tinylab.org>
> ---
>
> target/riscv/csr.c | 62 ++++++++++++++++++++++++----------------------
> 1 file changed, 32 insertions(+), 30 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index c2dd9d5af0..cc74819759 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -963,7 +963,7 @@ static RISCVException sstc_32(CPURISCVState *env, int csrno)
> }
>
> static RISCVException read_vstimecmp(CPURISCVState *env, int csrno,
> - target_ulong *val)
> + target_ulong *val)
> {
> *val = env->vstimecmp;
>
> @@ -971,7 +971,7 @@ static RISCVException read_vstimecmp(CPURISCVState *env, int csrno,
> }
>
> static RISCVException read_vstimecmph(CPURISCVState *env, int csrno,
> - target_ulong *val)
> + target_ulong *val)
> {
> *val = env->vstimecmp >> 32;
>
> @@ -979,7 +979,7 @@ static RISCVException read_vstimecmph(CPURISCVState *env, int csrno,
> }
>
> static RISCVException write_vstimecmp(CPURISCVState *env, int csrno,
> - target_ulong val)
> + target_ulong val)
> {
> RISCVCPU *cpu = env_archcpu(env);
>
> @@ -996,7 +996,7 @@ static RISCVException write_vstimecmp(CPURISCVState *env, int csrno,
> }
>
> static RISCVException write_vstimecmph(CPURISCVState *env, int csrno,
> - target_ulong val)
> + target_ulong val)
> {
> RISCVCPU *cpu = env_archcpu(env);
>
> @@ -1020,7 +1020,7 @@ static RISCVException read_stimecmp(CPURISCVState *env, int csrno,
> }
>
> static RISCVException read_stimecmph(CPURISCVState *env, int csrno,
> - target_ulong *val)
> + target_ulong *val)
> {
> if (riscv_cpu_virt_enabled(env)) {
> *val = env->vstimecmp >> 32;
> @@ -1032,7 +1032,7 @@ static RISCVException read_stimecmph(CPURISCVState *env, int csrno,
> }
>
> static RISCVException write_stimecmp(CPURISCVState *env, int csrno,
> - target_ulong val)
> + target_ulong val)
> {
> RISCVCPU *cpu = env_archcpu(env);
>
> @@ -1055,7 +1055,7 @@ static RISCVException write_stimecmp(CPURISCVState *env, int csrno,
> }
>
> static RISCVException write_stimecmph(CPURISCVState *env, int csrno,
> - target_ulong val)
> + target_ulong val)
> {
> RISCVCPU *cpu = env_archcpu(env);
>
> @@ -1342,7 +1342,8 @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
>
> /* 'E' excludes all other extensions */
> if (val & RVE) {
> - /* when we support 'E' we can do "val = RVE;" however
> + /*
> + * when we support 'E' we can do "val = RVE;" however
> * for now we just drop writes if 'E' is present.
> */
> return RISCV_EXCP_NONE;
> @@ -1364,7 +1365,8 @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
> val &= ~RVD;
> }
>
> - /* Suppress 'C' if next instruction is not aligned
> + /*
> + * Suppress 'C' if next instruction is not aligned
> * TODO: this should check next_pc
> */
> if ((val & RVC) && (GETPC() & ~3) != 0) {
> @@ -1833,28 +1835,28 @@ static RISCVException write_mscratch(CPURISCVState *env, int csrno,
> }
>
> static RISCVException read_mepc(CPURISCVState *env, int csrno,
> - target_ulong *val)
> + target_ulong *val)
> {
> *val = env->mepc;
> return RISCV_EXCP_NONE;
> }
>
> static RISCVException write_mepc(CPURISCVState *env, int csrno,
> - target_ulong val)
> + target_ulong val)
> {
> env->mepc = val;
> return RISCV_EXCP_NONE;
> }
>
> static RISCVException read_mcause(CPURISCVState *env, int csrno,
> - target_ulong *val)
> + target_ulong *val)
> {
> *val = env->mcause;
> return RISCV_EXCP_NONE;
> }
>
> static RISCVException write_mcause(CPURISCVState *env, int csrno,
> - target_ulong val)
> + target_ulong val)
> {
> env->mcause = val;
> return RISCV_EXCP_NONE;
> @@ -1876,14 +1878,14 @@ static RISCVException write_mtval(CPURISCVState *env, int csrno,
>
> /* Execution environment configuration setup */
> static RISCVException read_menvcfg(CPURISCVState *env, int csrno,
> - target_ulong *val)
> + target_ulong *val)
> {
> *val = env->menvcfg;
> return RISCV_EXCP_NONE;
> }
>
> static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
> - target_ulong val)
> + target_ulong val)
> {
> uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCFG_CBZE;
>
> @@ -1896,14 +1898,14 @@ static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
> }
>
> static RISCVException read_menvcfgh(CPURISCVState *env, int csrno,
> - target_ulong *val)
> + target_ulong *val)
> {
> *val = env->menvcfg >> 32;
> return RISCV_EXCP_NONE;
> }
>
> static RISCVException write_menvcfgh(CPURISCVState *env, int csrno,
> - target_ulong val)
> + target_ulong val)
> {
> uint64_t mask = MENVCFG_PBMTE | MENVCFG_STCE;
> uint64_t valh = (uint64_t)val << 32;
> @@ -1914,7 +1916,7 @@ static RISCVException write_menvcfgh(CPURISCVState *env, int csrno,
> }
>
> static RISCVException read_senvcfg(CPURISCVState *env, int csrno,
> - target_ulong *val)
> + target_ulong *val)
> {
> RISCVException ret;
>
> @@ -1928,7 +1930,7 @@ static RISCVException read_senvcfg(CPURISCVState *env, int csrno,
> }
>
> static RISCVException write_senvcfg(CPURISCVState *env, int csrno,
> - target_ulong val)
> + target_ulong val)
> {
> uint64_t mask = SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCFG_CBZE;
> RISCVException ret;
> @@ -1943,7 +1945,7 @@ static RISCVException write_senvcfg(CPURISCVState *env, int csrno,
> }
>
> static RISCVException read_henvcfg(CPURISCVState *env, int csrno,
> - target_ulong *val)
> + target_ulong *val)
> {
> RISCVException ret;
>
> @@ -1957,7 +1959,7 @@ static RISCVException read_henvcfg(CPURISCVState *env, int csrno,
> }
>
> static RISCVException write_henvcfg(CPURISCVState *env, int csrno,
> - target_ulong val)
> + target_ulong val)
> {
> uint64_t mask = HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCFG_CBZE;
> RISCVException ret;
> @@ -1977,7 +1979,7 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno,
> }
>
> static RISCVException read_henvcfgh(CPURISCVState *env, int csrno,
> - target_ulong *val)
> + target_ulong *val)
> {
> RISCVException ret;
>
> @@ -1991,7 +1993,7 @@ static RISCVException read_henvcfgh(CPURISCVState *env, int csrno,
> }
>
> static RISCVException write_henvcfgh(CPURISCVState *env, int csrno,
> - target_ulong val)
> + target_ulong val)
> {
> uint64_t mask = HENVCFG_PBMTE | HENVCFG_STCE;
> uint64_t valh = (uint64_t)val << 32;
> @@ -2034,13 +2036,13 @@ static RISCVException write_mstateen0(CPURISCVState *env, int csrno,
> }
>
> static RISCVException write_mstateen_1_3(CPURISCVState *env, int csrno,
> - target_ulong new_val)
> + target_ulong new_val)
> {
> return write_mstateen(env, csrno, SMSTATEEN_STATEEN, new_val);
> }
>
> static RISCVException read_mstateenh(CPURISCVState *env, int csrno,
> - target_ulong *val)
> + target_ulong *val)
> {
> *val = env->mstateen[csrno - CSR_MSTATEEN0H] >> 32;
>
> @@ -2061,7 +2063,7 @@ static RISCVException write_mstateenh(CPURISCVState *env, int csrno,
> }
>
> static RISCVException write_mstateen0h(CPURISCVState *env, int csrno,
> - target_ulong new_val)
> + target_ulong new_val)
> {
> uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
>
> @@ -2069,7 +2071,7 @@ static RISCVException write_mstateen0h(CPURISCVState *env, int csrno,
> }
>
> static RISCVException write_mstateenh_1_3(CPURISCVState *env, int csrno,
> - target_ulong new_val)
> + target_ulong new_val)
> {
> return write_mstateenh(env, csrno, SMSTATEEN_STATEEN, new_val);
> }
> @@ -2106,7 +2108,7 @@ static RISCVException write_hstateen0(CPURISCVState *env, int csrno,
> }
>
> static RISCVException write_hstateen_1_3(CPURISCVState *env, int csrno,
> - target_ulong new_val)
> + target_ulong new_val)
> {
> return write_hstateen(env, csrno, SMSTATEEN_STATEEN, new_val);
> }
> @@ -2145,7 +2147,7 @@ static RISCVException write_hstateen0h(CPURISCVState *env, int csrno,
> }
>
> static RISCVException write_hstateenh_1_3(CPURISCVState *env, int csrno,
> - target_ulong new_val)
> + target_ulong new_val)
> {
> return write_hstateenh(env, csrno, SMSTATEEN_STATEEN, new_val);
> }
> @@ -3338,7 +3340,7 @@ static RISCVException read_mseccfg(CPURISCVState *env, int csrno,
> }
>
> static RISCVException write_mseccfg(CPURISCVState *env, int csrno,
> - target_ulong val)
> + target_ulong val)
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Zhiwei
> {
> mseccfg_csr_write(env, val);
> return RISCV_EXCP_NONE;
next prev parent reply other threads:[~2023-02-17 2:24 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-13 18:01 [PATCH 00/18] target/riscv: Various fixes to gdbstub and CSR access Bin Meng
2023-02-13 18:01 ` [PATCH 01/18] target/riscv: gdbstub: Check priv spec version before reporting CSR Bin Meng
2023-02-14 8:40 ` weiwei
2023-02-17 2:11 ` LIU Zhiwei
2023-02-13 18:01 ` [PATCH 02/18] target/riscv: Correct the priority policy of riscv_csrrw_check() Bin Meng
2023-02-14 8:43 ` weiwei
2023-02-17 2:15 ` LIU Zhiwei
2023-02-13 18:01 ` [PATCH 03/18] target/riscv: gdbstub: Minor change for better readability Bin Meng
2023-02-14 8:45 ` weiwei
2023-02-17 2:20 ` LIU Zhiwei
2023-02-13 18:02 ` [PATCH 04/18] target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled Bin Meng
2023-02-14 8:46 ` weiwei
2023-02-17 2:23 ` LIU Zhiwei
2023-02-13 18:02 ` [PATCH 05/18] target/riscv: Coding style fixes in csr.c Bin Meng
2023-02-14 8:48 ` weiwei
2023-02-17 2:24 ` LIU Zhiwei [this message]
2023-02-13 18:02 ` [PATCH 06/18] target/riscv: Use 'bool' type for read_only Bin Meng
2023-02-14 8:48 ` weiwei
2023-02-17 2:24 ` LIU Zhiwei
2023-02-13 18:02 ` [PATCH 07/18] target/riscv: Simplify {read, write}_pmpcfg() a little bit Bin Meng
2023-02-14 8:50 ` [PATCH 07/18] target/riscv: Simplify {read,write}_pmpcfg() " weiwei
2023-02-17 2:26 ` LIU Zhiwei
2023-02-13 18:02 ` [PATCH 08/18] target/riscv: Simplify getting RISCVCPU pointer from env Bin Meng
2023-02-14 8:51 ` weiwei
2023-02-17 2:30 ` LIU Zhiwei
2023-02-13 18:02 ` [PATCH 09/18] target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64 Bin Meng
2023-02-14 8:56 ` weiwei
2023-02-17 2:36 ` LIU Zhiwei
2023-02-13 18:02 ` [PATCH 10/18] target/riscv: gdbstub: Turn on debugger mode before calling CSR predicate() Bin Meng
2023-02-14 9:02 ` weiwei
2023-02-17 2:39 ` LIU Zhiwei
2023-02-13 18:02 ` [PATCH 11/18] target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml Bin Meng
2023-02-14 9:13 ` weiwei
2023-02-17 2:43 ` LIU Zhiwei
2023-02-13 19:19 ` [PATCH 00/18] target/riscv: Various fixes to gdbstub and CSR access Daniel Henrique Barboza
2023-02-14 14:31 ` Bin Meng
2023-02-14 1:09 ` [PATCH 12/18] target/riscv: Allow debugger to access user timer and counter CSRs Bin Meng
2023-02-14 9:16 ` weiwei
2023-02-17 2:48 ` LIU Zhiwei
2023-02-14 1:09 ` [PATCH 13/18] target/riscv: Allow debugger to access seed CSR Bin Meng
2023-02-14 9:18 ` weiwei
2023-02-17 2:59 ` LIU Zhiwei
2023-02-14 3:06 ` [PATCH 14/18] target/riscv: Allow debugger to access {h, s}stateen CSRs Bin Meng
2023-02-14 9:24 ` weiwei
2023-02-14 4:12 ` [PATCH 15/18] target/riscv: Allow debugger to access sstc CSRs Bin Meng
2023-02-14 9:26 ` weiwei
2023-02-14 4:12 ` [PATCH 16/18] target/riscv: Drop priv level check in mseccfg predicate() Bin Meng
2023-02-14 9:26 ` weiwei
2023-02-14 4:31 ` [PATCH 17/18] target/riscv: Group all predicate() routines together Bin Meng
2023-02-14 9:27 ` weiwei
2023-02-14 14:27 ` [PATCH 18/18] target/riscv: Move configuration check to envcfg CSRs predicate() Bin Meng
2023-02-14 14:59 ` weiwei
2023-02-15 2:22 ` Bin Meng
2023-02-15 2:57 ` weiwei
2023-02-16 16:40 ` Palmer Dabbelt
2023-02-17 1:59 ` Bin Meng
2023-02-17 17:28 ` Palmer Dabbelt
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