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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-11df7703bd7sm70475024c88.10.2025.12.09.00.14.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 09 Dec 2025 00:14:20 -0800 (PST) Message-ID: <9f338aa0-efc6-4fa7-add6-fdfaf39ca954@redhat.com> Date: Tue, 9 Dec 2025 09:14:10 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 14/33] hw/arm/smmuv3-accel: Add nested vSTE install/uninstall support Content-Language: en-US To: Shameer Kolothum , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, jgg@nvidia.com, nicolinc@nvidia.com, ddutile@redhat.com, berrange@redhat.com, nathanc@nvidia.com, mochs@nvidia.com, smostafa@google.com, wangzhou1@hisilicon.com, jiangkunkun@huawei.com, jonathan.cameron@huawei.com, zhangfei.gao@linaro.org, zhenzhong.duan@intel.com, yi.l.liu@intel.com, kjaju@nvidia.com References: <20251120132213.56581-1-skolothumtho@nvidia.com> <20251120132213.56581-15-skolothumtho@nvidia.com> From: Eric Auger In-Reply-To: <20251120132213.56581-15-skolothumtho@nvidia.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 11/20/25 2:21 PM, Shameer Kolothum wrote: > From: Nicolin Chen > > A device placed behind a vSMMU instance must have corresponding vSTEs > (bypass, abort, or translate) installed. The bypass and abort proxy nested > HWPTs are pre-allocated. > > For translate HWPT, a vDEVICE object is allocated and associated with the > vIOMMU for each guest device. This allows the host kernel to establish a > virtual SID to physical SID mapping, which is required for handling > invalidations and event reporting. > > The translate HWPT is allocated based on the guest STE configuration and > attached to the device when the guest issues SMMU_CMD_CFGI_STE or > SMMU_CMD_CFGI_STE_RANGE, provided the STE enables S1 translation. > > If the guest STE is invalid or S1 translation is disabled, the device is > attached to one of the pre-allocated ABORT or BYPASS HWPTs instead. > > While at it, export smmu_find_ste() for use here. > > Signed-off-by: Nicolin Chen > Signed-off-by: Shameer Kolothum > Reviewed-by: Jonathan Cameron > Signed-off-by: Shameer Kolothum > --- > hw/arm/smmuv3-accel.c | 197 +++++++++++++++++++++++++++++++++++++++ > hw/arm/smmuv3-accel.h | 22 +++++ > hw/arm/smmuv3-internal.h | 20 ++++ > hw/arm/smmuv3.c | 11 ++- > hw/arm/trace-events | 2 + > 5 files changed, 250 insertions(+), 2 deletions(-) > > diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c > index 4dd56a8e65..2e42d2d484 100644 > --- a/hw/arm/smmuv3-accel.c > +++ b/hw/arm/smmuv3-accel.c > @@ -51,6 +51,188 @@ static uint32_t smmuv3_accel_gbpa_hwpt(SMMUv3State *s, SMMUv3AccelState *accel) > accel->abort_hwpt_id : accel->bypass_hwpt_id; > } > > +static bool > +smmuv3_accel_alloc_vdev(SMMUv3AccelDevice *accel_dev, int sid, Error **errp) > +{ > + SMMUv3AccelState *accel = accel_dev->s_accel; > + HostIOMMUDeviceIOMMUFD *idev = accel_dev->idev; > + IOMMUFDVdev *vdev = accel_dev->vdev; > + uint32_t vdevice_id; > + > + if (!idev || vdev) { > + return true; > + } > + > + if (!iommufd_backend_alloc_vdev(idev->iommufd, idev->devid, > + accel->viommu.viommu_id, sid, > + &vdevice_id, errp)) { > + return false; > + } > + > + vdev = g_new(IOMMUFDVdev, 1); > + vdev->vdevice_id = vdevice_id; > + vdev->virt_id = sid; > + accel_dev->vdev = vdev; > + return true; > +} > + > +static SMMUS1Hwpt * > +smmuv3_accel_dev_alloc_translate(SMMUv3AccelDevice *accel_dev, STE *ste, > + Error **errp) > +{ > + uint64_t ste_0 = (uint64_t)ste->word[0] | (uint64_t)ste->word[1] << 32; > + uint64_t ste_1 = (uint64_t)ste->word[2] | (uint64_t)ste->word[3] << 32; > + HostIOMMUDeviceIOMMUFD *idev = accel_dev->idev; > + SMMUv3AccelState *accel = accel_dev->s_accel; > + struct iommu_hwpt_arm_smmuv3 nested_data = { > + .ste = { > + cpu_to_le64(ste_0 & STE0_MASK), > + cpu_to_le64(ste_1 & STE1_MASK), > + }, > + }; > + uint32_t hwpt_id = 0, flags = 0; > + SMMUS1Hwpt *s1_hwpt; > + > + if (!iommufd_backend_alloc_hwpt(idev->iommufd, idev->devid, > + accel->viommu.viommu_id, flags, > + IOMMU_HWPT_DATA_ARM_SMMUV3, > + sizeof(nested_data), &nested_data, > + &hwpt_id, errp)) { > + return NULL; > + } > + > + s1_hwpt = g_new0(SMMUS1Hwpt, 1); > + s1_hwpt->hwpt_id = hwpt_id; > + trace_smmuv3_accel_translate_ste(accel_dev->vdev->virt_id, hwpt_id, > + nested_data.ste[1], nested_data.ste[0]); > + return s1_hwpt; > +} > + > +bool smmuv3_accel_install_ste(SMMUv3State *s, SMMUDevice *sdev, int sid, > + Error **errp) > +{ > + SMMUEventInfo event = {.type = SMMU_EVT_NONE, .sid = sid, > + .inval_ste_allowed = true}; > + SMMUv3AccelState *accel = s->s_accel; > + SMMUv3AccelDevice *accel_dev; > + HostIOMMUDeviceIOMMUFD *idev; > + uint32_t config, hwpt_id = 0; > + SMMUS1Hwpt *s1_hwpt = NULL; > + const char *type; > + STE ste; > + > + if (!accel) { > + return true; > + } > + > + accel_dev = container_of(sdev, SMMUv3AccelDevice, sdev); > + if (!accel_dev->s_accel) { > + return true; > + } > + > + idev = accel_dev->idev; > + if (!smmuv3_accel_alloc_vdev(accel_dev, sid, errp)) { > + return false; > + } > + > + if (smmu_find_ste(sdev->smmu, sid, &ste, &event)) { > + /* No STE found, nothing to install */ > + return true; > + } > + > + /* > + * Install the STE based on SMMU enabled/config: > + * - attach a pre-allocated HWPT for abort/bypass > + * - or a new HWPT for translate STE > + * > + * Note: The vdev remains associated with accel_dev even if HWPT > + * attach/alloc fails, since the Guest-Host SID mapping stays > + * valid as long as the device is behind the accelerated SMMUv3. > + */ > + if (!smmu_enabled(s)) { > + hwpt_id = smmuv3_accel_gbpa_hwpt(s, accel); > + } else { > + config = STE_CONFIG(&ste); > + > + if (!STE_VALID(&ste) || STE_CFG_ABORT(config)) { > + hwpt_id = accel->abort_hwpt_id; > + } else if (STE_CFG_BYPASS(config)) { > + hwpt_id = accel->bypass_hwpt_id; > + } else if (STE_CFG_S1_TRANSLATE(config)) { > + s1_hwpt = smmuv3_accel_dev_alloc_translate(accel_dev, &ste, errp); > + if (!s1_hwpt) { > + return false; > + } > + hwpt_id = s1_hwpt->hwpt_id; > + } > + } > + > + if (!hwpt_id) { > + error_setg(errp, "Invalid STE config for sid 0x%x", > + smmu_get_sid(&accel_dev->sdev)); > + return false; > + } > + > + if (!host_iommu_device_iommufd_attach_hwpt(idev, hwpt_id, errp)) { > + if (s1_hwpt) { > + iommufd_backend_free_id(idev->iommufd, s1_hwpt->hwpt_id); > + g_free(s1_hwpt); > + } > + return false; > + } > + > + /* Free the previous s1_hwpt */ > + if (accel_dev->s1_hwpt) { > + iommufd_backend_free_id(idev->iommufd, accel_dev->s1_hwpt->hwpt_id); > + g_free(accel_dev->s1_hwpt); > + } > + > + accel_dev->s1_hwpt = s1_hwpt; > + if (hwpt_id == accel->abort_hwpt_id) { > + type = "abort"; > + } else if (hwpt_id == accel->bypass_hwpt_id) { > + type = "bypass"; > + } else { > + type = "translate"; > + } > + > + trace_smmuv3_accel_install_ste(sid, type, hwpt_id); > + return true; > +} > + > +bool smmuv3_accel_install_ste_range(SMMUv3State *s, SMMUSIDRange *range, > + Error **errp) > +{ > + SMMUv3AccelState *accel = s->s_accel; > + SMMUv3AccelDevice *accel_dev; > + Error *local_err = NULL; > + bool all_ok = true; > + > + if (!accel) { > + return true; > + } > + > + QLIST_FOREACH(accel_dev, &accel->device_list, next) { > + uint32_t sid = smmu_get_sid(&accel_dev->sdev); > + > + if (sid >= range->start && sid <= range->end) { > + if (!smmuv3_accel_install_ste(s, &accel_dev->sdev, > + sid, &local_err)) { > + error_append_hint(&local_err, "Device 0x%x: Failed to install " > + "STE\n", sid); > + error_report_err(local_err); > + local_err = NULL; > + all_ok = false; > + } > + } > + } > + > + if (!all_ok) { > + error_setg(errp, "Failed to install all STEs properly"); > + } > + return all_ok; > +} > + > static bool > smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev, > Error **errp) > @@ -161,6 +343,7 @@ static void smmuv3_accel_unset_iommu_device(PCIBus *bus, void *opaque, > HostIOMMUDeviceIOMMUFD *idev; > SMMUv3AccelDevice *accel_dev; > SMMUv3AccelState *accel; > + IOMMUFDVdev *vdev; > SMMUDevice *sdev; > > if (!sbus) { > @@ -181,6 +364,20 @@ static void smmuv3_accel_unset_iommu_device(PCIBus *bus, void *opaque, > "0x%x", idev->devid); > } > > + if (accel_dev->s1_hwpt) { > + iommufd_backend_free_id(accel_dev->idev->iommufd, > + accel_dev->s1_hwpt->hwpt_id); > + g_free(accel_dev->s1_hwpt); > + accel_dev->s1_hwpt = NULL; > + } > + > + vdev = accel_dev->vdev; > + if (vdev) { > + iommufd_backend_free_id(accel->viommu.iommufd, vdev->vdevice_id); > + g_free(vdev); > + accel_dev->vdev = NULL; > + } > + > accel_dev->idev = NULL; > accel_dev->s_accel = NULL; > QLIST_REMOVE(accel_dev, next); > diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h > index c72605caab..ae896cfa8b 100644 > --- a/hw/arm/smmuv3-accel.h > +++ b/hw/arm/smmuv3-accel.h > @@ -25,19 +25,41 @@ typedef struct SMMUv3AccelState { > QLIST_HEAD(, SMMUv3AccelDevice) device_list; > } SMMUv3AccelState; > > +typedef struct SMMUS1Hwpt { > + uint32_t hwpt_id; > +} SMMUS1Hwpt; > + > typedef struct SMMUv3AccelDevice { > SMMUDevice sdev; > HostIOMMUDeviceIOMMUFD *idev; > + SMMUS1Hwpt *s1_hwpt; > + IOMMUFDVdev *vdev; > QLIST_ENTRY(SMMUv3AccelDevice) next; > SMMUv3AccelState *s_accel; > } SMMUv3AccelDevice; > > #ifdef CONFIG_ARM_SMMUV3_ACCEL > void smmuv3_accel_init(SMMUv3State *s); > +bool smmuv3_accel_install_ste(SMMUv3State *s, SMMUDevice *sdev, int sid, > + Error **errp); > +bool smmuv3_accel_install_ste_range(SMMUv3State *s, SMMUSIDRange *range, > + Error **errp); > #else > static inline void smmuv3_accel_init(SMMUv3State *s) > { > } > +static inline bool > +smmuv3_accel_install_ste(SMMUv3State *s, SMMUDevice *sdev, int sid, > + Error **errp) > +{ > + return true; > +} > +static inline bool > +smmuv3_accel_install_ste_range(SMMUv3State *s, SMMUSIDRange *range, > + Error **errp) > +{ > + return true; > +} > #endif > > #endif /* HW_ARM_SMMUV3_ACCEL_H */ > diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h > index 81212a58f1..a76e4e2484 100644 > --- a/hw/arm/smmuv3-internal.h > +++ b/hw/arm/smmuv3-internal.h > @@ -547,6 +547,8 @@ typedef struct CD { > uint32_t word[16]; > } CD; > > +int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, SMMUEventInfo *event); > + > /* STE fields */ > > #define STE_VALID(x) extract32((x)->word[0], 0, 1) > @@ -556,6 +558,7 @@ typedef struct CD { > #define STE_CFG_S2_ENABLED(config) (config & 0x2) > #define STE_CFG_ABORT(config) (!(config & 0x4)) > #define STE_CFG_BYPASS(config) (config == 0x4) > +#define STE_CFG_S1_TRANSLATE(config) (config == 0x5) > > #define STE_S1FMT(x) extract32((x)->word[0], 4 , 2) > #define STE_S1CDMAX(x) extract32((x)->word[1], 27, 5) > @@ -586,6 +589,23 @@ typedef struct CD { > #define SMMU_STE_VALID (1ULL << 0) > #define SMMU_STE_CFG_BYPASS (1ULL << 3) > > +#define STE0_V MAKE_64BIT_MASK(0, 1) > +#define STE0_CONFIG MAKE_64BIT_MASK(1, 3) > +#define STE0_S1FMT MAKE_64BIT_MASK(4, 2) > +#define STE0_CTXPTR MAKE_64BIT_MASK(6, 50) > +#define STE0_S1CDMAX MAKE_64BIT_MASK(59, 5) > +#define STE0_MASK (STE0_S1CDMAX | STE0_CTXPTR | STE0_S1FMT | STE0_CONFIG | \ > + STE0_V) > + > +#define STE1_S1DSS MAKE_64BIT_MASK(0, 2) > +#define STE1_S1CIR MAKE_64BIT_MASK(2, 2) > +#define STE1_S1COR MAKE_64BIT_MASK(4, 2) > +#define STE1_S1CSH MAKE_64BIT_MASK(6, 2) > +#define STE1_S1STALLD MAKE_64BIT_MASK(27, 1) > +#define STE1_EATS MAKE_64BIT_MASK(28, 2) > +#define STE1_MASK (STE1_EATS | STE1_S1STALLD | STE1_S1CSH | STE1_S1COR | \ > + STE1_S1CIR | STE1_S1DSS) > + > static inline int oas2bits(int oas_field) > { > switch (oas_field) { > diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c > index 374ae08baa..bfb41b8866 100644 > --- a/hw/arm/smmuv3.c > +++ b/hw/arm/smmuv3.c > @@ -630,8 +630,7 @@ bad_ste: > * Supports linear and 2-level stream table > * Return 0 on success, -EINVAL otherwise > */ > -static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, > - SMMUEventInfo *event) > +int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, SMMUEventInfo *event) > { > dma_addr_t addr, strtab_base; > uint32_t log2size; > @@ -1341,6 +1340,10 @@ static int smmuv3_cmdq_consume(SMMUv3State *s, Error **errp) > } > > trace_smmuv3_cmdq_cfgi_ste(sid); > + if (!smmuv3_accel_install_ste(s, sdev, sid, errp)) { > + cmd_error = SMMU_CERROR_ILL; > + break; > + } > smmuv3_flush_config(sdev); > > break; > @@ -1361,6 +1364,10 @@ static int smmuv3_cmdq_consume(SMMUv3State *s, Error **errp) > sid_range.end = sid_range.start + mask; > > trace_smmuv3_cmdq_cfgi_ste_range(sid_range.start, sid_range.end); > + if (!smmuv3_accel_install_ste_range(s, &sid_range, errp)) { > + cmd_error = SMMU_CERROR_ILL; > + break; > + } > smmu_configs_inv_sid_range(bs, sid_range); > break; > } > diff --git a/hw/arm/trace-events b/hw/arm/trace-events > index 2aaa0c40c7..8135c0c734 100644 > --- a/hw/arm/trace-events > +++ b/hw/arm/trace-events > @@ -69,6 +69,8 @@ smmu_reset_exit(void) "" > #smmuv3-accel.c > smmuv3_accel_set_iommu_device(int devfn, uint32_t devid) "devfn=0x%x (idev devid=0x%x)" > smmuv3_accel_unset_iommu_device(int devfn, uint32_t devid) "devfn=0x%x (idev devid=0x%x)" > +smmuv3_accel_translate_ste(uint32_t vsid, uint32_t hwpt_id, uint64_t ste_1, uint64_t ste_0) "vSID=0x%x hwpt_id=0x%x ste=%"PRIx64":%"PRIx64 > +smmuv3_accel_install_ste(uint32_t vsid, const char * type, uint32_t hwpt_id) "vSID=0x%x ste type=%s hwpt_id=0x%x" > > # strongarm.c > strongarm_uart_update_parameters(const char *label, int speed, char parity, int data_bits, int stop_bits) "%s speed=%d parity=%c data=%d stop=%d" Reviewed-by: Eric Auger Eric