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([2602:47:d48c:8101:9d81:5b04:51d7:acae]) by smtp.gmail.com with ESMTPSA id e188-20020a621ec5000000b0058200ef9caesm1481889pfe.39.2023.01.06.11.29.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 06 Jan 2023 11:29:41 -0800 (PST) Message-ID: <9f9a6c22-315b-de1e-958e-89963c5e7e90@linaro.org> Date: Fri, 6 Jan 2023 11:29:39 -0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [RFC PATCH 00/40] Toward class init of cpu features Content-Language: en-US To: Peter Maydell Cc: qemu-devel@nongnu.org, pbonzini@redhat.com, berrange@redhat.com, eduardo@habkost.net, armbru@redhat.com, ajones@ventanamicro.com, alex.bennee@linaro.org References: <20230103181646.55711-1-richard.henderson@linaro.org> From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -49 X-Spam_score: -5.0 X-Spam_bar: ----- X-Spam_report: (-5.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-2.939, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 1/6/23 11:12, Peter Maydell wrote: > The trouble with this idea is that not all instances of the same > class are actually necessarily the same. For instance, if you > have a system with both (a) a Cortex-A53 with a PMU, and > (b) a Cortex-A53 without a PMU, then they're both instances of > the same class, but they shouldn't be sharing the coprocessor > register hashtable because they don't have an identical set of > system registers. > > This kind of same-CPU-type-heterogenous-configuration system is > not something we're currently using on A-profile, but we do have > it for M-profile (the sse200 has a dual-core setup where only one > of the CPUs has an FPU), so it's not totally outlandish. Yes, I know. See patch 29 where I moved the vfp and dsp properties off of the m-profile cpus and created new cpu classes instead, specifically for the sse220. It's not scalable, I'll grant you, but it's hard to design for something we're not using. What we use now, apart from the sse200, are common properties set on the command-line. If we were presented with the class properties early enough, we could create sub-classes with the desired properties before instantiating the objects that go with. Anyway, it seems like we ought to have some solution that does not involve repeating the same id register finalization + cpregs hash table construction per cpu -- especially for user-only. r~