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Wed, 26 Feb 2020 03:03:19 +0000 (UTC) Received: from [10.72.13.217] (ovpn-13-217.pek2.redhat.com [10.72.13.217]) by smtp.corp.redhat.com (Postfix) with ESMTP id BC29760BE1; Wed, 26 Feb 2020 03:03:09 +0000 (UTC) Subject: Re: [PATCH] hw/net/imx_fec: write TGSR and TCSR3 in imx_enet_write() To: Peter Maydell References: <20200225025923.19328-1-kuhn.chenqun@huawei.com> <9206dda7-0e12-b68e-87ca-1985b61381bc@redhat.com> From: Jason Wang Message-ID: <9fc2581c-56a1-0969-6a13-1454a1865264@redhat.com> Date: Wed, 26 Feb 2020 11:03:04 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 205.139.110.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: zhanghailiang , QEMU Trivial , QEMU Developers , qemu-arm , Peter Chubb , Chen Qun Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 2020/2/25 =E4=B8=8B=E5=8D=886:18, Peter Maydell wrote: > On Tue, 25 Feb 2020 at 05:41, Jason Wang wrote: >> >> On 2020/2/25 =E4=B8=8A=E5=8D=8810:59, Chen Qun wrote: >>> The current code causes clang static code analyzer generate warning: >>> hw/net/imx_fec.c:858:9: warning: Value stored to 'value' is never read >>> value =3D value & 0x0000000f; >>> ^ ~~~~~~~~~~~~~~~~~~ >>> hw/net/imx_fec.c:864:9: warning: Value stored to 'value' is never read >>> value =3D value & 0x000000fd; >>> ^ ~~~~~~~~~~~~~~~~~~ >>> >>> According to the definition of the function, the two =E2=80=9Cvalue=E2= =80=9D assignments >>> should be written to registers. >>> >>> Reported-by: Euler Robot >>> Signed-off-by: Chen Qun >>> --- >>> I'm not sure if this modification is correct, just from the function >>> definition, it is correct. >>> --- >>> hw/net/imx_fec.c | 4 ++-- >>> 1 file changed, 2 insertions(+), 2 deletions(-) >>> >>> diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c >>> index 6a124a154a..92f6215712 100644 >>> --- a/hw/net/imx_fec.c >>> +++ b/hw/net/imx_fec.c >>> @@ -855,13 +855,13 @@ static void imx_enet_write(IMXFECState *s, uint32= _t index, uint32_t value) >>> break; >>> case ENET_TGSR: >>> /* implement clear timer flag */ >>> - value =3D value & 0x0000000f; >>> + s->regs[index] =3D value & 0x0000000f; >>> break; > Hi; the datasheet for this SoC says that these bits > of the register are write-1-to-clear, so while this > is definitely a bug I don't think this is the right fix. > >>> case ENET_TCSR0: >>> case ENET_TCSR1: >>> case ENET_TCSR2: >>> case ENET_TCSR3: >>> - value =3D value & 0x000000fd; >>> + s->regs[index] =3D value & 0x000000fd; >>> break; > Here bit 7 is write-1-to-clear, though bits 0 and > 2..5 are simple write-the-value. > >>> case ENET_TCCR0: >>> case ENET_TCCR1: >> >> Applied. > Could you drop this from your queue, please? > > thanks > -- PMM Sure, Chen please send V2 to address Peter's comment. Thanks