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[174.21.76.141]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fb17d8093esm34799395ad.3.2024.07.04.08.18.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 04 Jul 2024 08:18:27 -0700 (PDT) Message-ID: <9fe81eeb-473a-4ffb-ad6f-f93e40283e8a@linaro.org> Date: Thu, 4 Jul 2024 08:18:25 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 0/2] target/arm: Fix unwind from dc zva and FEAT_MOPS To: Ilya Leoshkevich , qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, david@redhat.com, balaton@eik.bme.hu References: <20240702234155.2106399-1-richard.henderson@linaro.org> <13b19a4859e25274d05663bc0ca05621c56af985.camel@linux.ibm.com> Content-Language: en-US From: Richard Henderson In-Reply-To: <13b19a4859e25274d05663bc0ca05621c56af985.camel@linux.ibm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 7/4/24 07:50, Ilya Leoshkevich wrote: > On Tue, 2024-07-02 at 16:41 -0700, Richard Henderson wrote: >> While looking into Zoltan's attempt to speed up ppc64 DCBZ >> (data cache block set to zero), I wondered what AArch64 was >> doing differently.  It turned out that Arm is the only user >> of tlb_vaddr_to_host. >> >> None of the code sequences in use between AArch64, Power64 and S390X >> are 100% safe, with race conditions vs mmap et al, however, AArch64 >> is the only one that will fail this single threaded test case.  Use >> of these new functions fixes the race condition as well, though I >> have not yet touched the other guests. >> >> I thought about exposing accel/tcg/user-retaddr.h for direct use >> from the targets, but perhaps these wrappers are cleaner.  RFC? >> >> >> r~ >> >> >> Richard Henderson (2): >>   accel/tcg: Introduce memset_ra, memmove_ra >>   target/arm: Use memset_ra, memmove_ra in helper-a64.c >> >>  include/exec/cpu_ldst.h            | 40 ++++++++++++++++ >>  accel/tcg/user-exec.c              | 22 +++++++++ >>  target/arm/tcg/helper-a64.c        | 10 ++-- >>  tests/tcg/multiarch/memset-fault.c | 77 >> ++++++++++++++++++++++++++++++ >>  4 files changed, 144 insertions(+), 5 deletions(-) >>  create mode 100644 tests/tcg/multiarch/memset-fault.c > > This sounds good to me. > > I haven't debugged it, but I wonder why doesn't s390x fail here. > For XC with src == dst, it does access_memset() -> do_access_memset() > -> memset() without setting the RA. And I don't think that anything > around it sets the RA either. s390x uses probe_access_flags, which verifies the page is mapped and writable, and raises the exception when it isn't. In contrast, for user-only, tlb_vaddr_to_host *only* performs the guest -> host address mapping, i.e. (addr + guest_base). r~