messages from 2021-12-09 19:56:37 to 2021-12-10 15:32:37 UTC [more...]
[PATCH v1] Add dummy Aspeed AST2600 Display Port MCU (DPMCU)
2021-12-10 15:13 UTC (5+ messages)
[PATCH 0/2] RISC-V: Populate mtval and stval
2021-12-10 15:28 UTC (5+ messages)
` [PATCH 1/2] target/riscv: Set the opcode in DisasContext
` [PATCH 2/2] target/riscv: Implement the stval/mtval illegal instruction
Redesign of QEMU startup & initial configuration
2021-12-10 15:26 UTC (12+ messages)
[PATCH 0/4] target/ppc: Fix VSX instructions register access
2021-12-10 14:13 UTC (5+ messages)
` [PATCH 1/4] target/ppc: Fix xs{max,min}[cj]dp to use VSX registers
` [PATCH 2/4] target/ppc: Move xs{max,min}[cj]dp to decodetree
` [PATCH 3/4] target/ppc: fix xscvqpdp register access
` [PATCH 4/4] target/ppc: move xscvqpdp to decodetree
[PATCH v1] Add dummy Aspeed AST2600 Display Port MCU (DPMCU)
2021-12-10 8:04 UTC
[PATCH v4 00/11] Xilinx Versal's PMC SLCR and OSPI support
2021-12-10 15:17 UTC (9+ messages)
` [PATCH v4 01/11] hw/misc: Add a model of Versal's PMC SLCR
` [PATCH v4 02/11] hw/arm/xlnx-versal: Connect "
` [PATCH v4 04/11] hw/dma: Add the DMA control interface
` [PATCH v4 11/11] docs/devel: Add documentation for "
[PATCH 0/3] iotests: multiprocessing!!
2021-12-10 14:47 UTC (11+ messages)
` [PATCH 1/3] iotests/testrunner.py: add doc string for run_test()
` [PATCH 2/3] iotests/testrunner.py: move updating last_elapsed to run_tests
` [PATCH 3/3] iotests: check: multiprocessing support
[PATCH v5 00/31] block layer: split block APIs in global state and I/O
2021-12-10 14:38 UTC (5+ messages)
` [PATCH v5 04/31] include/sysemu/block-backend: split header into I/O and global state (GS) API
` [PATCH v5 05/31] block-backend: special comments for blk_set/get_perm due to fuse
[PATCH v10 00/10] acpi: Error Record Serialization Table, ERST, support for QEMU
2021-12-10 14:18 UTC (3+ messages)
` [PATCH v10 05/10] ACPI ERST: support for ACPI ERST feature
[PATCH 0/2] scsi: to fix issue on passing host_status to the guest kernel
2021-12-10 14:16 UTC (3+ messages)
` [PATCH 1/2] scsi/scsi_bus: use host_status as parameter for scsi_sense_from_host_status()
` [PATCH 2/2] scsi/utils: pass host_status = SCSI_HOST_ERROR to guest kernel
[PATCH v9 00/10] acpi: Error Record Serialization Table, ERST, support for QEMU
2021-12-10 14:09 UTC (5+ messages)
` [PATCH v9 05/10] ACPI ERST: support for ACPI ERST feature
[RFC] block-backend: prevent dangling BDS pointer in blk_drain()
2021-12-10 14:00 UTC (2+ messages)
[PATCH v4 0/3] hw/block/fdc: Fix CVE-2021-20196
2021-12-10 13:42 UTC (2+ messages)
[PATCH 0/8] virtio: Add vhost-user based Video decode
2021-12-10 13:23 UTC (10+ messages)
` [PATCH 5/8] standard-headers: Add virtio_video.h
` [PATCH 6/8] virtio_video: Add Fast Walsh-Hadamard Transform format
[PATCH 0/2] iotests: Fix crypto algorithm failures
2021-12-10 13:15 UTC (4+ messages)
` [PATCH 2/2] iotests/149: Skip on unsupported ciphers
[PATCH v2] Move the libssh setup from configure to meson.build
2021-12-10 13:05 UTC (5+ messages)
[PATCH] tests/docker: add libfuse3 development headers
2021-12-10 12:39 UTC (2+ messages)
[PATCH] uas: add missing return
2021-12-10 12:26 UTC (2+ messages)
[PATCH v6 0/6] MSG_ZEROCOPY + multifd
2021-12-10 12:15 UTC (3+ messages)
` [PATCH v6 1/6] QIOChannel: Add io_writev_zero_copy & io_flush_zero_copy callbacks
[PATCH for-7.0] gitlab-ci: Add cirrus-ci based tests for NetBSD and OpenBSD
2021-12-10 12:10 UTC (2+ messages)
[PATCH] configure: remove DIRS
2021-12-10 11:59 UTC (3+ messages)
[PATCH] tests/tcg: use CONFIG_LINUX_USER, not CONFIG_LINUX
2021-12-10 11:48 UTC (3+ messages)
[PATCH] configure: remove dead variables
2021-12-10 11:44 UTC (3+ messages)
[RFC PATCH] blog post: how to get your new feature up-streamed
2021-12-10 10:51 UTC (2+ messages)
[PATCH v2 for-7.0] scripts: Explain the difference between linux-headers and standard-headers
2021-12-10 10:48 UTC (4+ messages)
[PATCH v3 00/23] Migration: Transmit and detect zero pages in the multifd threads
2021-12-10 10:41 UTC (4+ messages)
` [PATCH v3 18/23] multifd: Use normal pages array on the recv side
[PATCH v1 00/12] Add riscv kvm accel support
2021-12-10 10:11 UTC (26+ messages)
` [PATCH v1 03/12] target/riscv: Implement function kvm_arch_init_vcpu
` [PATCH v1 04/12] target/riscv: Implement kvm_arch_get_registers
` [PATCH v1 05/12] target/riscv: Implement kvm_arch_put_registers
` [PATCH v1 06/12] target/riscv: Support start kernel directly by KVM
` [PATCH v1 07/12] target/riscv: Support setting external interrupt "
` [PATCH v1 08/12] target/riscv: Handle KVM_EXIT_RISCV_SBI exit
` [PATCH v1 10/12] target/riscv: Add kvm_riscv_get/put_regs_timer
` [PATCH v1 12/12] target/riscv: Support virtual time context synchronization
[PATCH v2 00/12] Add riscv kvm accel support
2021-12-10 10:07 UTC (13+ messages)
` [PATCH v2 01/12] update-linux-headers: Add asm-riscv/kvm.h
` [PATCH v2 02/12] target/riscv: Add target/riscv/kvm.c to place the public kvm interface
` [PATCH v2 03/12] target/riscv: Implement function kvm_arch_init_vcpu
` [PATCH v2 04/12] target/riscv: Implement kvm_arch_get_registers
` [PATCH v2 05/12] target/riscv: Implement kvm_arch_put_registers
` [PATCH v2 06/12] target/riscv: Support start kernel directly by KVM
` [PATCH v2 07/12] target/riscv: Support setting external interrupt "
` [PATCH v2 08/12] target/riscv: Handle KVM_EXIT_RISCV_SBI exit
` [PATCH v2 09/12] target/riscv: Add host cpu type
` [PATCH v2 10/12] target/riscv: Add kvm_riscv_get/put_regs_timer
` [PATCH v2 11/12] target/riscv: Implement virtual time adjusting with vm state changing
` [PATCH v2 12/12] target/riscv: Support virtual time context synchronization
[PATCH 0/4] configure and meson.build improvements
2021-12-10 10:10 UTC (7+ messages)
` [PATCH 3/4] Move CONFIG_XFS handling to meson.build
[RFC PATCH v2 00/44] TDX support
2021-12-10 9:54 UTC (4+ messages)
` [RFC PATCH v2 34/44] target/i386/tdx: set reboot action to shutdown when tdx
RFC for NBD protocol extension: extended headers
2021-12-10 8:16 UTC (3+ messages)
` [libnbd PATCH 00/13] libnbd patches for NBD_OPT_EXTENDED_HEADERS
` [Libguestfs] "
[PATCH v11 00/77] support vector extension v1.0
2021-12-10 7:57 UTC (78+ messages)
` [PATCH v11 01/77] target/riscv: drop vector 0.7.1 and add 1.0 support
` [PATCH v11 02/77] target/riscv: Use FIELD_EX32() to extract wd field
` [PATCH v11 03/77] target/riscv: rvv-1.0: add mstatus VS field
` [PATCH v11 04/77] target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty
` [PATCH v11 05/77] target/riscv: rvv-1.0: add sstatus VS field
` [PATCH v11 06/77] target/riscv: rvv-1.0: introduce writable misa.v field
` [PATCH v11 07/77] target/riscv: rvv-1.0: add translation-time vector context status
` [PATCH v11 08/77] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers
` [PATCH v11 09/77] target/riscv: rvv-1.0: add vcsr register
` [PATCH v11 10/77] target/riscv: rvv-1.0: add vlenb register
` [PATCH v11 11/77] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers
` [PATCH v11 12/77] target/riscv: rvv-1.0: remove MLEN calculations
` [PATCH v11 13/77] target/riscv: rvv-1.0: add fractional LMUL
` [PATCH v11 14/77] target/riscv: rvv-1.0: add VMA and VTA
` [PATCH v11 15/77] target/riscv: rvv-1.0: update check functions
` [PATCH v11 16/77] target/riscv: introduce more imm value modes in translator functions
` [PATCH v11 17/77] target/riscv: rvv:1.0: add translation-time nan-box helper function
` [PATCH v11 18/77] target/riscv: rvv-1.0: remove amo operations instructions
` [PATCH v11 19/77] target/riscv: rvv-1.0: configure instructions
` [PATCH v11 20/77] target/riscv: rvv-1.0: stride load and store instructions
` [PATCH v11 21/77] target/riscv: rvv-1.0: index "
` [PATCH v11 22/77] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns
` [PATCH v11 23/77] target/riscv: rvv-1.0: fault-only-first unit stride load
` [PATCH v11 24/77] target/riscv: rvv-1.0: load/store whole register instructions
` [PATCH v11 25/77] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns
` [PATCH v11 26/77] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation
` [PATCH v11 27/77] target/riscv: rvv-1.0: floating-point square-root instruction
` [PATCH v11 28/77] target/riscv: rvv-1.0: floating-point classify instructions
` [PATCH v11 29/77] target/riscv: rvv-1.0: count population in mask instruction
` [PATCH v11 30/77] target/riscv: rvv-1.0: find-first-set mask bit instruction
` [PATCH v11 31/77] target/riscv: rvv-1.0: set-X-first mask bit instructions
` [PATCH v11 32/77] target/riscv: rvv-1.0: iota instruction
` [PATCH v11 33/77] target/riscv: rvv-1.0: element index instruction
` [PATCH v11 34/77] target/riscv: rvv-1.0: allow load element with sign-extended
` [PATCH v11 35/77] target/riscv: rvv-1.0: register gather instructions
` [PATCH v11 36/77] target/riscv: rvv-1.0: integer scalar move instructions
` [PATCH v11 37/77] target/riscv: rvv-1.0: floating-point move instruction
` [PATCH v11 38/77] target/riscv: rvv-1.0: floating-point scalar move instructions
` [PATCH v11 39/77] target/riscv: rvv-1.0: whole register "
` [PATCH v11 40/77] target/riscv: rvv-1.0: integer extension instructions
` [PATCH v11 41/77] target/riscv: rvv-1.0: single-width averaging add and subtract instructions
` [PATCH v11 42/77] target/riscv: rvv-1.0: single-width bit shift instructions
` [PATCH v11 43/77] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow
` [PATCH v11 44/77] target/riscv: rvv-1.0: narrowing integer right shift instructions
` [PATCH v11 45/77] target/riscv: rvv-1.0: widening integer multiply-add instructions
` [PATCH v11 46/77] target/riscv: rvv-1.0: single-width saturating add and subtract instructions
` [PATCH v11 47/77] target/riscv: rvv-1.0: integer comparison instructions
` [PATCH v11 48/77] target/riscv: rvv-1.0: floating-point compare instructions
` [PATCH v11 49/77] target/riscv: rvv-1.0: mask-register logical instructions
` [PATCH v11 50/77] target/riscv: rvv-1.0: slide instructions
` [PATCH v11 51/77] target/riscv: rvv-1.0: floating-point "
` [PATCH v11 52/77] target/riscv: rvv-1.0: narrowing fixed-point clip instructions
` [PATCH v11 53/77] target/riscv: rvv-1.0: single-width floating-point reduction
` [PATCH v11 54/77] target/riscv: rvv-1.0: widening floating-point reduction instructions
` [PATCH v11 55/77] target/riscv: rvv-1.0: single-width scaling shift instructions
` [PATCH v11 56/77] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add
` [PATCH v11 57/77] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf
` [PATCH v11 58/77] target/riscv: rvv-1.0: remove integer extract instruction
` [PATCH v11 59/77] target/riscv: rvv-1.0: floating-point min/max instructions
` [PATCH v11 60/77] target/riscv: introduce floating-point rounding mode enum
` [PATCH v11 61/77] target/riscv: rvv-1.0: floating-point/integer type-convert instructions
` [PATCH v11 62/77] target/riscv: rvv-1.0: widening floating-point/integer type-convert
` [PATCH v11 63/77] target/riscv: add "set round to odd" rounding mode helper function
` [PATCH v11 64/77] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert
` [PATCH v11 65/77] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits
` [PATCH v11 66/77] target/riscv: rvv-1.0: implement vstart CSR
` [PATCH v11 67/77] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid
` [PATCH v11 68/77] target/riscv: gdb: support vector registers for rv64 & rv32
` [PATCH v11 69/77] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction
` [PATCH v11 70/77] target/riscv: rvv-1.0: floating-point reciprocal "
` [PATCH v11 71/77] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11
` [PATCH v11 72/77] target/riscv: rvv-1.0: add vsetivli instruction
` [PATCH v11 73/77] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()
` [PATCH v11 74/77] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns
` [PATCH v11 75/77] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm
` [PATCH v11 76/77] target/riscv: rvv-1.0: update opivv_vadc_check() comment
` [PATCH v11 77/77] target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructions
[PATCH v6 0/8] target/riscv: support Zfh, Zfhmin extension v0.1
2021-12-10 7:43 UTC (9+ messages)
` [PATCH v6 1/8] target/riscv: zfh: half-precision load and store
` [PATCH v6 2/8] target/riscv: zfh: half-precision computational
` [PATCH v6 3/8] target/riscv: zfh: half-precision convert and move
` [PATCH v6 4/8] target/riscv: zfh: half-precision floating-point compare
` [PATCH v6 5/8] target/riscv: zfh: half-precision floating-point classify
` [PATCH v6 6/8] target/riscv: zfh: add Zfh cpu property
` [PATCH v6 7/8] target/riscv: zfh: implement zfhmin extension
` [PATCH v6 8/8] target/riscv: zfh: add Zfhmin cpu property
[PATCH v10 00/77] support vector extension v1.0
2021-12-10 7:35 UTC (3+ messages)
[PATCH 0/7] A collection of RISC-V cleanups and improvements
2021-12-10 7:10 UTC (6+ messages)
` [PATCH 1/7] hw/intc: sifive_plic: Add a reset function
` [PATCH 7/7] hw/riscv: Use error_fatal for SoC realisation
[PATCH v7 0/7] Add vmnet.framework based network backend
2021-12-10 6:23 UTC (3+ messages)
` [PATCH v7 2/7] net/vmnet: add vmnet backends to qapi/net
[PATCH] COLO: Move some trace code behind qemu_mutex_unlock_iothread()
2021-12-10 22:14 UTC
[PATCH v6 00/18] Adding partial support for 128-bit riscv target
2021-12-10 2:03 UTC (3+ messages)
` [PATCH v6 09/18] target/riscv: accessors to registers upper part and 128-bit load/store
[PATCH v2 1/4] target/i386: Fix sanity check on max APIC ID / X2APIC enablement
2021-12-09 22:08 UTC (4+ messages)
` [PATCH v2 2/4] intel_iommu: Support IR-only mode without DMA translation
` [PATCH v2 3/4] intel_iommu: Only allow interrupt remapping to be enabled if it's supported
` [PATCH v2 4/4] intel_iommu: Fix irqchip / X2APIC configuration checks
[PATCH 0/1] uas: add stream number sanity checks (maybe 6.1)
2021-12-09 20:16 UTC (3+ messages)
` [PATCH 1/1] uas: add stream number sanity checks
[PATCH v2] target/i386: Use assert() to sanity-check b1 in SSE decode
2021-12-09 20:01 UTC (6+ messages)
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).