messages from 2021-12-13 15:34:35 to 2021-12-14 13:20:20 UTC [more...]
[PATCH v7 00/15] linux-user: simplify safe signal handling
2021-12-14 13:13 UTC (21+ messages)
` [PATCH v7 01/15] linux-user: Untabify all safe-syscall.inc.S
` [PATCH v7 02/15] linux-user: Move syscall error detection into safe_syscall_base
` [PATCH v7 03/15] linux-user/host/mips: Add safe-syscall.inc.S
` [PATCH v7 04/15] linux-user/host/sparc64: "
` [PATCH v7 05/15] linux-user: Remove HAVE_SAFE_SYSCALL and hostdep.h
` [PATCH v7 06/15] linux-user: Rename TARGET_ERESTARTSYS to QEMU_ERESTARTSYS
` [PATCH v7 07/15] bsd-user: "
` [PATCH v7 08/15] linux-user: Rename TARGET_QEMU_ESIGRETURN to QEMU_ESIGRETURN
` [PATCH v7 09/15] linux-user: Create special-errno.h
` [PATCH v7 10/15] bsd-user: "
` [PATCH v7 11/15] common-user: Move safe-syscall.* from linux-user
` [PATCH v7 12/15] common-user: Adjust system call return on FreeBSD
` [PATCH v7 13/15] linux-user: Move thunk.c from top-level
` [PATCH v7 14/15] meson: Move linux_user_ss to linux-user/
` [PATCH v7 15/15] meson: Move bsd_user_ss to bsd-user/
[PATCH v2 0/4] hw/display: QOM'ify vga_mmio_init() as TYPE_VGA_MMIO
2021-12-14 13:07 UTC (8+ messages)
` [PATCH v2 3/4] hw/display/vga-mmio: "
Redesign of QEMU startup & initial configuration
2021-12-14 13:05 UTC (25+ messages)
` Meeting today?
[PATCH] Relax X509 CA cert sanity checking
2021-12-14 13:04 UTC (2+ messages)
[RFC] vhost-vdpa-net: add vhost-vdpa-net host device support
2021-12-14 13:03 UTC (16+ messages)
[PATCH v2 0/6] gqa-win: get_pci_info: Fix memory leak
2021-12-14 12:41 UTC (7+ messages)
` [PATCH v2 1/6] gqa-win: get_pci_info: Clean dev_info if handle is valid
` [PATCH v2 2/6] gqa-win: get_pci_info: Use common 'end' label
` [PATCH v2 3/6] gqa-win: get_pci_info: Free parent_dev_info properly
` [PATCH v2 4/6] gqa-win: get_pci_info: Split logic to separate functions
` [PATCH v2 5/6] gqa-win: get_pci_info: Add g_autofree for few variables
` [PATCH v2 6/6] gqa-win: get_pci_info: Replace 'while' with 2 calls of the function
[PATCH v2] MAINTAINERS: Change my email address
2021-12-14 12:38 UTC (9+ messages)
[RFC PATCH 00/12] QOM/QAPI integration part 1
2021-12-14 11:52 UTC (8+ messages)
` [RFC PATCH 02/12] qom: Create object_configure()
[PATCH v4 00/11] Xilinx Versal's PMC SLCR and OSPI support
2021-12-14 11:03 UTC (13+ messages)
` [PATCH v4 01/11] hw/misc: Add a model of Versal's PMC SLCR
` [PATCH v4 02/11] hw/arm/xlnx-versal: Connect "
` [PATCH v4 06/11] hw/ssi: Add a model of Xilinx Versal's OSPI flash memory controller
` [PATCH v4 11/11] docs/devel: Add documentation for the DMA control interface
[PATCH v10 0/3] support dirty restraint on vCPU
2021-12-14 11:07 UTC (4+ messages)
` [PATCH v10 1/3] migration/dirtyrate: implement vCPU dirtyrate calculation periodically
` [PATCH v10 2/3] cpu-throttle: implement virtual CPU throttle
` [PATCH v10 3/3] cpus-common: implement dirty page limit on virtual CPU
[PATCH v5 00/12] Xilinx Versal's PMC SLCR and OSPI support
2021-12-14 11:03 UTC (13+ messages)
` [PATCH v5 01/12] hw/misc: Add a model of Versal's PMC SLCR
` [PATCH v5 02/12] hw/arm/xlnx-versal: 'Or' the interrupts from the BBRAM and RTC models
` [PATCH v5 03/12] hw/arm/xlnx-versal: Connect Versal's PMC SLCR
` [PATCH v5 04/12] include/hw/dma/xlnx_csu_dma: Add in missing includes in the header
` [PATCH v5 05/12] hw/dma: Add the DMA control interface
` [PATCH v5 06/12] hw/dma/xlnx_csu_dma: Implement "
` [PATCH v5 07/12] hw/ssi: Add a model of Xilinx Versal's OSPI flash memory controller
` [PATCH v5 08/12] hw/arm/xlnx-versal: Connect the OSPI flash memory controller model
` [PATCH v5 09/12] hw/block/m25p80: Add support for Micron Xccela flash mt35xu01g
` [PATCH v5 10/12] hw/arm/xlnx-versal-virt: Connect mt35xu01g flashes to the OSPI
` [PATCH v5 11/12] MAINTAINERS: Add an entry for Xilinx Versal OSPI
` [PATCH v5 12/12] docs/devel: Add documentation for the DMA control interface
[PATCH 0/4] configure and meson.build improvements
2021-12-14 9:15 UTC (8+ messages)
` [PATCH 3/4] Move CONFIG_XFS handling to meson.build
[PATCH v1] Add dummy Aspeed AST2600 Display Port MCU (DPMCU)
2021-12-14 8:19 UTC (6+ messages)
[PATCH v9 00/31] LoongArch64 port of QEMU TCG
2021-12-14 8:01 UTC (32+ messages)
` [PATCH v9 01/31] elf: Add machine type value for LoongArch
` [PATCH v9 02/31] MAINTAINERS: Add tcg/loongarch64 entry with myself as maintainer
` [PATCH v9 03/31] tcg/loongarch64: Add the tcg-target.h file
` [PATCH v9 04/31] tcg/loongarch64: Add generated instruction opcodes and encoding helpers
` [PATCH v9 05/31] tcg/loongarch64: Add register names, allocation order and input/output sets
` [PATCH v9 06/31] tcg/loongarch64: Define the operand constraints
` [PATCH v9 07/31] tcg/loongarch64: Implement necessary relocation operations
` [PATCH v9 08/31] tcg/loongarch64: Implement the memory barrier op
` [PATCH v9 09/31] tcg/loongarch64: Implement tcg_out_mov and tcg_out_movi
` [PATCH v9 10/31] tcg/loongarch64: Implement goto_ptr
` [PATCH v9 11/31] tcg/loongarch64: Implement sign-/zero-extension ops
` [PATCH v9 12/31] tcg/loongarch64: Implement not/and/or/xor/nor/andc/orc ops
` [PATCH v9 13/31] tcg/loongarch64: Implement deposit/extract ops
` [PATCH v9 14/31] tcg/loongarch64: Implement bswap{16,32,64} ops
` [PATCH v9 15/31] tcg/loongarch64: Implement clz/ctz ops
` [PATCH v9 16/31] tcg/loongarch64: Implement shl/shr/sar/rotl/rotr ops
` [PATCH v9 17/31] tcg/loongarch64: Implement add/sub ops
` [PATCH v9 18/31] tcg/loongarch64: Implement mul/mulsh/muluh/div/divu/rem/remu ops
` [PATCH v9 19/31] tcg/loongarch64: Implement br/brcond ops
` [PATCH v9 20/31] tcg/loongarch64: Implement setcond ops
` [PATCH v9 21/31] tcg/loongarch64: Implement tcg_out_call
` [PATCH v9 22/31] tcg/loongarch64: Implement simple load/store ops
` [PATCH v9 23/31] tcg/loongarch64: Add softmmu load/store helpers, implement qemu_ld/qemu_st ops
` [PATCH v9 24/31] tcg/loongarch64: Implement tcg_target_qemu_prologue
` [PATCH v9 25/31] tcg/loongarch64: Implement exit_tb/goto_tb
` [PATCH v9 26/31] tcg/loongarch64: Implement tcg_target_init
` [PATCH v9 27/31] tcg/loongarch64: Register the JIT
` [PATCH v9 28/31] common-user: Add safe syscall handling for loongarch64 hosts
` [PATCH v9 29/31] linux-user: Implement CPU-specific signal handler "
` [PATCH v9 30/31] configure, meson.build: Mark support "
` [PATCH v9 31/31] tests/docker: Add gentoo-loongarch64-cross image and run cross builds in GitLab
[PATCH v2] COLO: Move some trace code behind qemu_mutex_unlock_iothread()
2021-12-14 17:19 UTC (2+ messages)
[PATCH] MAINTAINERS: Change my email address
2021-12-14 7:40 UTC
[PATCH] hw/riscv: Use load address rather than entry point for fw_dynamic next_addr
2021-12-14 3:24 UTC
[PATCH v9 00/10] acpi: Error Record Serialization Table, ERST, support for QEMU
2021-12-14 3:14 UTC (7+ messages)
` [PATCH v9 05/10] ACPI ERST: support for ACPI ERST feature
[PATCH v10 00/10] acpi: Error Record Serialization Table, ERST, support for QEMU
2021-12-14 2:58 UTC (8+ messages)
` [PATCH v10 06/10] ACPI ERST: build the ACPI ERST table
[RFC PATCH v3 00/27] Add LoongArch softmmu support
2021-12-14 1:08 UTC (4+ messages)
[PATCH] Target/arm: Implement Cortex-A5
2021-12-13 22:34 UTC (6+ messages)
[PATCH v2 0/2] target/hppa: Fix deposit assert from trans_shrpw_imm
2021-12-13 22:22 UTC (4+ messages)
` [PATCH v2 1/2] target/hppa: Minor code movement
` [PATCH v2 2/2] target/hppa: Fix deposit assert from trans_shrpw_imm
[RFC PATCH] target/ppc: do not silence snan in xscvspdpn
2021-12-13 22:19 UTC (6+ messages)
update hexagon float ref files
2021-12-13 21:39 UTC (3+ messages)
[RFC PATCH v5 0/1] s390x: Improvements to SIGP handling [QEMU]
2021-12-13 21:09 UTC (2+ messages)
` [RFC PATCH v5 1/1] s390x: sigp: Reorder the SIGP STOP code
[PATCH v4 0/7] nbd reconnect on open
2021-12-13 20:50 UTC (7+ messages)
` [PATCH v4 1/7] nbd: allow reconnect on open, with corresponding new options
` [PATCH v4 2/7] nbd/client-connection: nbd_co_establish_connection(): return real error
` [PATCH v4 5/7] For qemu_io* functions support --image-opts argument, which conflicts with -f argument from qemu_io_args
` [PATCH v4 6/7] Add qemu-io Popen constructor wrapper. To be used in the following new test commit
` [PATCH v4 7/7] iotests: add nbd-reconnect-on-open test
[PATCH] target/ppc: Fix e6500 boot
2021-12-13 19:51 UTC (2+ messages)
[PATCH 0/5] gqa-win: get_pci_info: Fix memory leak
2021-12-13 19:50 UTC (11+ messages)
` [PATCH 1/5] gqa-win: get_pci_info: Clean dev_info if handle is valid
` [PATCH 2/5] gqa-win: get_pci_info: Use common 'cleanup' label
` [PATCH 3/5] gqa-win: get_pci_info: Free parent_dev_info properly
` [PATCH 4/5] gqa-win: get_pci_info: Replace 'while' with 2 calls of the function
` [PATCH 5/5] gqa-win: get_pci_info: Add g_autofree for few variables
[PATCH v2 00/19] ppc/pnv: Add support for user created PHB3/PHB4 devices
2021-12-13 18:39 UTC (9+ messages)
` [PATCH v2 01/19] ppc/pnv: Change the maximum of PHB3 devices for Power8NVL
` [PATCH v2 03/19] ppc/pnv: Use the chip class to check the index of PHB3 devices
` [PATCH v2 06/19] ppc/pnv: Use QOM hierarchy to scan "
` [PATCH v2 14/19] ppc/pnv: Use QOM hierarchy to scan PEC PHB4 devices
[PATCH v7 0/8] virtio-iommu: Add ACPI support (Arm part + tests)
2021-12-13 17:50 UTC (2+ messages)
[PATCH] target/hppa: Fix deposit assert from trans_shrpw_imm
2021-12-13 17:42 UTC
[PATCH v7 00/18] Adding partial support for 128-bit riscv target
2021-12-13 16:38 UTC (19+ messages)
` [PATCH v7 01/18] exec/memop: Adding signedness to quad definitions
` [PATCH v7 02/18] exec/memop: Adding signed quad and octo defines
` [PATCH v7 03/18] qemu/int128: addition of div/rem 128-bit operations
` [PATCH v7 04/18] target/riscv: additional macros to check instruction support
` [PATCH v7 05/18] target/riscv: separation of bitwise logic and arithmetic helpers
` [PATCH v7 06/18] target/riscv: array for the 64 upper bits of 128-bit registers
` [PATCH v7 07/18] target/riscv: setup everything for rv64 to support rv128 execution
` [PATCH v7 08/18] target/riscv: moving some insns close to similar insns
` [PATCH v7 09/18] target/riscv: accessors to registers upper part and 128-bit load/store
` [PATCH v7 10/18] target/riscv: support for 128-bit bitwise instructions
` [PATCH v7 11/18] target/riscv: support for 128-bit U-type instructions
` [PATCH v7 12/18] target/riscv: support for 128-bit shift instructions
` [PATCH v7 13/18] target/riscv: support for 128-bit arithmetic instructions
` [PATCH v7 14/18] target/riscv: support for 128-bit M extension
` [PATCH v7 15/18] target/riscv: adding high part of some csrs
` [PATCH v7 16/18] target/riscv: helper functions to wrap calls to 128-bit csr insns
` [PATCH v7 17/18] target/riscv: modification of the trans_csrxx for 128-bit support
` [PATCH v7 18/18] target/riscv: actual functions to realize crs 128-bit insns
[PATCH] hw/i386: fix phys-bits on cpus with AMD SEV/SMD
2021-12-13 16:59 UTC
[PATCH v3 0/6] aio-posix: split poll check from ready handler
2021-12-13 16:01 UTC (2+ messages)
[PATCH v2 0/4] block: minor refactoring in preparation to the block layer API split
2021-12-13 15:41 UTC (10+ messages)
` [PATCH v2 1/4] block_int: make bdrv_backing_overridden static
` [PATCH v2 2/4] include/sysemu/blockdev.c: introduce block_if_name
` [PATCH v2 3/4] include/sysemu/blockdev.h: move drive_add and inline drive_def
` [PATCH v2 4/4] include/sysemu/blockdev.h: remove drive_get_max_devs
[PATCH 00/26] arm gicv3 ITS: Various bug fixes and refactorings
2021-12-13 15:48 UTC (4+ messages)
` [PATCH 26/26] hw/intc/arm_gicv3_its: Factor out "find address of table entry" code
[PATCH] target/mips: Remove duplicated MIPSCPU::cp0_count_rate
2021-12-13 15:41 UTC (2+ messages)
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