messages from 2021-12-18 14:40:44 to 2021-12-20 16:12:55 UTC [more...]
[PULL 00/16] qtest and gitlab-CI improvements
2021-12-20 9:53 UTC (5+ messages)
Warnings during the virtio-net-failover test
2021-12-20 13:32 UTC (2+ messages)
[PATCH v2 0/8] migration: Postcopy cleanup on ram disgard
2021-12-20 8:53 UTC (3+ messages)
` [PATCH v2 2/8] migration: Don't return for postcopy_chunk_hostpages()
` [PATCH v2 4/8] migration: Do chunk page in postcopy_each_ram_send_discard()
[PATCH v4 0/7] nbd reconnect on open
2021-12-20 11:47 UTC (5+ messages)
` [PATCH v4 4/7] iotests.py: add qemu_tool_popen()
` [PATCH v4 6/7] Add qemu-io Popen constructor wrapper. To be used in the following new test commit
[PATCH v4 0/3] RISC-V: Populate mtval and stval
2021-12-20 6:49 UTC (4+ messages)
` [PATCH v4 1/3] target/riscv: Set the opcode in DisasContext
` [PATCH v4 2/3] target/riscv: Fixup setting GVA
` [PATCH v4 3/3] target/riscv: Implement the stval/mtval illegal instruction
[PATCH qemu] s390x/css: fix PMCW invalid mask
2021-12-20 12:11 UTC (6+ messages)
[PATCH 00/10] configure cleanups, mostly wrt $cpu and $targetos
2021-12-20 9:52 UTC (6+ messages)
` [PATCH 07/10] configure: unify x86_64 and x32
Virtio-GPU Xres and Yres seettings
2021-12-20 8:55 UTC (2+ messages)
[PULL 00/88] riscv-to-apply queue
2021-12-20 4:57 UTC (89+ messages)
` [PULL 01/88] target/riscv: zfh: half-precision load and store
` [PULL 02/88] target/riscv: zfh: half-precision computational
` [PULL 03/88] target/riscv: zfh: half-precision convert and move
` [PULL 04/88] target/riscv: zfh: half-precision floating-point compare
` [PULL 05/88] target/riscv: zfh: half-precision floating-point classify
` [PULL 06/88] target/riscv: zfh: add Zfh cpu property
` [PULL 07/88] target/riscv: zfh: implement zfhmin extension
` [PULL 08/88] target/riscv: zfh: add Zfhmin cpu property
` [PULL 09/88] target/riscv: drop vector 0.7.1 and add 1.0 support
` [PULL 10/88] target/riscv: Use FIELD_EX32() to extract wd field
` [PULL 11/88] target/riscv: rvv-1.0: add mstatus VS field
` [PULL 12/88] target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty
` [PULL 13/88] target/riscv: rvv-1.0: add sstatus VS field
` [PULL 14/88] target/riscv: rvv-1.0: introduce writable misa.v field
` [PULL 15/88] target/riscv: rvv-1.0: add translation-time vector context status
` [PULL 16/88] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers
` [PULL 17/88] target/riscv: rvv-1.0: add vcsr register
` [PULL 18/88] target/riscv: rvv-1.0: add vlenb register
` [PULL 19/88] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers
` [PULL 20/88] target/riscv: rvv-1.0: remove MLEN calculations
` [PULL 21/88] target/riscv: rvv-1.0: add fractional LMUL
` [PULL 22/88] target/riscv: rvv-1.0: add VMA and VTA
` [PULL 23/88] target/riscv: rvv-1.0: update check functions
` [PULL 24/88] target/riscv: introduce more imm value modes in translator functions
` [PULL 25/88] target/riscv: rvv:1.0: add translation-time nan-box helper function
` [PULL 26/88] target/riscv: rvv-1.0: remove amo operations instructions
` [PULL 27/88] target/riscv: rvv-1.0: configure instructions
` [PULL 28/88] target/riscv: rvv-1.0: stride load and store instructions
` [PULL 29/88] target/riscv: rvv-1.0: index "
` [PULL 30/88] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns
` [PULL 31/88] target/riscv: rvv-1.0: fault-only-first unit stride load
` [PULL 32/88] target/riscv: rvv-1.0: load/store whole register instructions
` [PULL 33/88] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns
` [PULL 34/88] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation
` [PULL 35/88] target/riscv: rvv-1.0: floating-point square-root instruction
` [PULL 36/88] target/riscv: rvv-1.0: floating-point classify instructions
` [PULL 37/88] target/riscv: rvv-1.0: count population in mask instruction
` [PULL 38/88] target/riscv: rvv-1.0: find-first-set mask bit instruction
` [PULL 39/88] target/riscv: rvv-1.0: set-X-first mask bit instructions
` [PULL 40/88] target/riscv: rvv-1.0: iota instruction
` [PULL 41/88] target/riscv: rvv-1.0: element index instruction
` [PULL 42/88] target/riscv: rvv-1.0: allow load element with sign-extended
` [PULL 43/88] target/riscv: rvv-1.0: register gather instructions
` [PULL 44/88] target/riscv: rvv-1.0: integer scalar move instructions
` [PULL 45/88] target/riscv: rvv-1.0: floating-point move instruction
` [PULL 46/88] target/riscv: rvv-1.0: floating-point scalar move instructions
` [PULL 47/88] target/riscv: rvv-1.0: whole register "
` [PULL 48/88] target/riscv: rvv-1.0: integer extension instructions
` [PULL 49/88] target/riscv: rvv-1.0: single-width averaging add and subtract instructions
` [PULL 50/88] target/riscv: rvv-1.0: single-width bit shift instructions
` [PULL 51/88] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow
` [PULL 52/88] target/riscv: rvv-1.0: narrowing integer right shift instructions
` [PULL 53/88] target/riscv: rvv-1.0: widening integer multiply-add instructions
` [PULL 54/88] target/riscv: rvv-1.0: single-width saturating add and subtract instructions
` [PULL 55/88] target/riscv: rvv-1.0: integer comparison instructions
` [PULL 56/88] target/riscv: rvv-1.0: floating-point compare instructions
` [PULL 57/88] target/riscv: rvv-1.0: mask-register logical instructions
` [PULL 58/88] target/riscv: rvv-1.0: slide instructions
` [PULL 59/88] target/riscv: rvv-1.0: floating-point "
` [PULL 60/88] target/riscv: rvv-1.0: narrowing fixed-point clip instructions
` [PULL 61/88] target/riscv: rvv-1.0: single-width floating-point reduction
` [PULL 62/88] target/riscv: rvv-1.0: widening floating-point reduction instructions
` [PULL 63/88] target/riscv: rvv-1.0: single-width scaling shift instructions
` [PULL 64/88] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add
` [PULL 65/88] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf
` [PULL 66/88] target/riscv: rvv-1.0: remove integer extract instruction
` [PULL 67/88] target/riscv: rvv-1.0: floating-point min/max instructions
` [PULL 68/88] target/riscv: introduce floating-point rounding mode enum
` [PULL 69/88] target/riscv: rvv-1.0: floating-point/integer type-convert instructions
` [PULL 70/88] target/riscv: rvv-1.0: widening floating-point/integer type-convert
` [PULL 71/88] target/riscv: add "set round to odd" rounding mode helper function
` [PULL 72/88] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert
` [PULL 73/88] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits
` [PULL 74/88] target/riscv: rvv-1.0: implement vstart CSR
` [PULL 75/88] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid
` [PULL 76/88] target/riscv: gdb: support vector registers for rv64 & rv32
` [PULL 77/88] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction
` [PULL 78/88] target/riscv: rvv-1.0: floating-point reciprocal "
` [PULL 79/88] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11
` [PULL 80/88] target/riscv: rvv-1.0: add vsetivli instruction
` [PULL 81/88] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()
` [PULL 82/88] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns
` [PULL 83/88] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm
` [PULL 84/88] target/riscv: rvv-1.0: update opivv_vadc_check() comment
` [PULL 85/88] target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructions
` [PULL 86/88] riscv: Set 5.4 as minimum kernel version for riscv32
` [PULL 87/88] target/riscv: Enable bitmanip Zb[abcs] instructions
` [PULL 88/88] hw/riscv: Use load address rather than entry point for fw_dynamic next_addr
[PULL 00/11] Ui 20210521 patches
2021-12-20 14:33 UTC (3+ messages)
` [PULL 09/11] ui/vnc: clipboard support
[PATCH 0/2] hw/nvme: Fix CVE-2021-3929 (DMA re-entrancy exploitation)
2021-12-20 6:40 UTC (4+ messages)
[PATCH] [RESEND] docs: Add spec of OVMF GUIDed table for SEV guests
2021-12-20 11:11 UTC
[PATCH] hw: m68k: Add virt compat machine type for 7.0
2021-12-20 6:45 UTC (2+ messages)
[PATCH v2 0/9] A collection of RISC-V cleanups and improvements
2021-12-20 5:41 UTC (9+ messages)
` [PATCH v2 5/9] target/riscv: Mark the Hypervisor extension as non experimental
` [PATCH v2 6/9] target/riscv: Enable the Hypervisor extension by default
` [PATCH v2 8/9] hw/riscv: virt: Allow support for 32 cores
[PULL 00/16] Misc patches for 2021-12-20
2021-12-20 4:47 UTC (18+ messages)
` [PULL 01/16] configure: make $targetos lowercase, use windows instead of MINGW32
` [PULL 02/16] configure: move target detection before CPU detection
` [PULL 03/16] configure: unify two case statements on $cpu
` [PULL 04/16] configure: unify ppc64 and ppc64le
` [PULL 05/16] configure: unify x86_64 and x32
` [PULL 06/16] meson: rename "arch" variable
` [PULL 07/16] configure, meson: move ARCH to meson.build
` [PULL 08/16] configure: remove unnecessary symlinks
` [PULL 09/16] configure: remove DIRS
` [PULL 10/16] meson: reenable test-fdmon-epoll
` [PULL 11/16] cpu: remove unnecessary #ifdef CONFIG_TCG
` [PULL 12/16] meson: add "check" argument to run_command
` [PULL 13/16] hw/scsi: Fix scsi_bus_init_named() docstring
` [PULL 14/16] hw/scsi/megasas: Fails command if SGL buffer overflows
` [PULL 15/16] tests/qtest/fuzz-megasas-test: Add test for GitLab issue #521
` [PULL 16/16] hw/i386/vmmouse: Require 'i8042' property to be set
[RFC] vhost-vdpa-net: add vhost-vdpa-net host device support
2021-12-20 2:48 UTC (12+ messages)
[PATCH v2 0/5] hw/qdev: Clarify qdev_connect_gpio_out() documentation
2021-12-20 2:14 UTC (9+ messages)
` [PATCH v2 1/5] hw/qdev: Cosmetic around documentation
` [PATCH v2 2/5] hw/qdev: Correct qdev_init_gpio_out_named() documentation
` [PATCH v2 3/5] hw/qdev: Correct qdev_connect_gpio_out_named() documentation
` [PATCH v2 5/5] hw/input/pckbd: Open-code i8042_setup_a20_line() wrapper
[PATCH 1/2] net/colo-compare.c: Optimize compare order for performance
2021-12-20 1:06 UTC (2+ messages)
` [PATCH 2/2] net/colo-compare.c: Update the default value comments
[PATCH] hw/nvram: at24 return 0xff if 1 byte address
2021-12-20 0:32 UTC
[PATCH v2] audio: Add sndio backend
2021-12-19 21:07 UTC (3+ messages)
[PATCH] linux-user/signal: Map exit signals in SIGCHLD siginfo_t
2021-12-19 18:47 UTC (4+ messages)
[PATCH] ui/gtk: Fix resolution change in fullscreen
2021-12-19 17:21 UTC
[PATCH 0/2] linux-user: fixes for sched_ syscalls
2021-12-19 17:19 UTC (5+ messages)
` [PATCH 1/2] linux-user: add sched_getattr support
` [PATCH 2/2] linux-user: call set/getscheduler set/getparam directly
[PATCH v2] linux-user: Mark cpu_loop() with noreturn attribute
2021-12-19 16:07 UTC (3+ messages)
[PATCH] linux-user/hexagon: Use generic target_stat64 structure
2021-12-19 16:04 UTC (2+ messages)
[PATCH 1/3] linux-user: netlink: update IFLA entries
2021-12-19 15:45 UTC (3+ messages)
` [PATCH 2/3] linux-user: netlink: Add IFLA_VFINFO_LIST
` [PATCH 3/3] linux-user: netlink: update IFLA_BRPORT entries
[PATCH 00/20] tcg: vector improvements
2021-12-19 11:37 UTC (25+ messages)
` [PATCH 01/20] tcg/optimize: Fix folding of vector ops
` [PATCH 02/20] tcg: Add opcodes for vector nand, nor, eqv
` [PATCH 03/20] tcg/ppc: Implement vector NAND, NOR, EQV
` [PATCH 04/20] tcg/s390x: "
` [PATCH 05/20] tcg/i386: Detect AVX512
` [PATCH 06/20] tcg/i386: Add tcg_out_evex_opc
` [PATCH 07/20] tcg/i386: Use tcg_can_emit_vec_op in expand_vec_cmp_noinv
` [PATCH 08/20] tcg/i386: Implement avx512 variable shifts
` [PATCH 09/20] tcg/i386: Implement avx512 scalar shift
` [PATCH 10/20] tcg/i386: Implement avx512 immediate sari shift
` [PATCH 11/20] tcg/i386: Implement avx512 immediate rotate
` [PATCH 12/20] tcg/i386: Implement avx512 variable rotate
` [PATCH 13/20] tcg/i386: Support avx512vbmi2 vector shift-double instructions
` [PATCH 14/20] tcg/i386: Expand vector word rotate as avx512vbmi2 shift-double
` [PATCH 15/20] tcg/i386: Remove rotls_vec from tcg_target_op_def
` [PATCH 16/20] tcg/i386: Expand scalar rotate with avx512 insns
` [PATCH 17/20] tcg/i386: Implement avx512 min/max/abs
` [PATCH 18/20] tcg/i386: Implement avx512 multiply
` [PATCH 19/20] tcg/i386: Implement more logical operations for avx512
` [PATCH 20/20] tcg/i386: Implement bitsel "
[PATCH 0/4] UI fixups
2021-12-19 2:30 UTC (5+ messages)
` [PATCH 1/4] ui: Use allocated size instead of window size
` [PATCH 2/4] ui: Remove unnecessary checks
` [PATCH 3/4] ui: Revert: "fix incorrect pointer position on highdpi with gtk"
` [PATCH 4/4] ui: Fix gtk/gl when the scaled virtual console does not fit the window
[RFC PATCH 0/3] hw/audio/intel-hda: Restrict DMA engine to memories (non-MMIO devices)
2021-12-18 16:14 UTC (5+ messages)
` [RFC PATCH 1/3] hw/audio/intel-hda: Do not ignore DMA overrun errors
` [RFC PATCH 2/3] hw/audio/intel-hda: Restrict DMA engine to memories (not MMIO devices)
` [RFC PATCH 3/3] tests/qtest/intel-hda-test: Add reproducer for issue #542
` [RFC PATCH 0/3] hw/audio/intel-hda: Restrict DMA engine to memories (CVE-2021-3611)
[PATCH 0/5] hw: Have DMA API take MemTxAttrs arg & propagate MemTxResult (part 4)
2021-12-18 15:10 UTC (6+ messages)
` [PATCH 1/5] hw/scsi/megasas: Use uint32_t for reply queue head/tail values
` [PATCH 2/5] dma: Let st*_pci_dma() take MemTxAttrs argument
` [PATCH 3/5] dma: Let ld*_pci_dma() "
` [PATCH 4/5] dma: Let st*_pci_dma() propagate MemTxResult
` [PATCH 5/5] dma: Let ld*_pci_dma() "
[PATCH v2] block: drop BLK_PERM_GRAPH_MOD
2021-12-18 15:04 UTC (3+ messages)
[PATCH 0/4] hw: Have DMA API take MemTxAttrs arg & propagate MemTxResult (part 3)
2021-12-18 14:51 UTC (5+ messages)
` [PATCH 1/4] dma: Let st*_dma() take MemTxAttrs argument
` [PATCH 2/4] dma: Let ld*_dma() "
` [PATCH 3/4] dma: Let st*_dma() propagate MemTxResult
` [PATCH 4/4] dma: Let ld*_dma() "
build qemu on Monterey?
2021-12-18 14:38 UTC
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