messages from 2023-05-05 00:52:00 to 2023-05-05 11:40:45 UTC [more...]
[PTACH v2 0/6] Add RISC-V KVM AIA Support
2023-05-05 11:39 UTC
[PULL 0/1] audio patch
2023-05-05 11:39 UTC
[RFC PATCH 0/4] spapr: clean up nested hv
2023-05-05 11:09 UTC (9+ messages)
` [RFC PATCH 1/4] spapr: H_ENTER_NESTED should restore host XER ca field
` [RFC PATCH 2/4] spapr: Add a nested state struct
` [RFC PATCH 3/4] spapr: load and store l2 state with helper functions
` [RFC PATCH 4/4] spapr: Move spapr nested HV to a new file
migration/rdma.c's macro ERROR()
2023-05-05 10:51 UTC
[PATCH v4 00/57] tcg: Improve atomicity support
2023-05-05 10:45 UTC (27+ messages)
` [PATCH v4 07/57] accel/tcg: Honor atomicity of stores
` [PATCH v4 08/57] target/loongarch: Do not include tcg-ldst.h
` [PATCH v4 09/57] tcg: Unify helper_{be,le}_{ld,st}*
` [PATCH v4 10/57] accel/tcg: Implement helper_{ld, st}*_mmu for user-only
` [PATCH v4 11/57] tcg/tci: Use helper_{ld,st}*_mmu "
` [PATCH v4 12/57] tcg: Add 128-bit guest memory primitives
` [PATCH v4 13/57] meson: Detect atomic128 support with optimization
` [PATCH v4 14/57] tcg/i386: Add have_atomic16
` [PATCH v4 15/57] accel/tcg: Use have_atomic16 in ldst_atomicity.c.inc
` [PATCH v4 17/57] tcg/aarch64: Detect have_lse, have_lse2 for linux
` [PATCH v4 18/57] tcg/aarch64: Detect have_lse, have_lse2 for darwin
` [PATCH v4 20/57] tcg: Introduce TCG_OPF_TYPE_MASK
` [PATCH v4 38/57] tcg/riscv: Support softmmu unaligned accesses
[PATCH] hw/ppc/Kconfig: NVDIMM is a hard requirement for the pseries machine
2023-05-05 10:41 UTC (4+ messages)
[PATCH] 9pfs/xen: Fix segfault on shutdown
2023-05-05 10:05 UTC (2+ messages)
[PATCH 0/4] vhost-user-fs: Internal migration
2023-05-05 9:53 UTC (6+ messages)
Question about graph locking preconditions regarding qemu_in_main_thread()
2023-05-05 9:35 UTC
[PATCH v4 0/2] tests/tcg/s390x: Enable the multiarch system tests
2023-05-05 9:31 UTC (3+ messages)
` [PATCH v4 1/2] tests/tcg/multiarch: Make the system memory test work on big-endian
` [PATCH v4 2/2] tests/tcg/s390x: Enable the multiarch system tests
[PATCH v20 00/21] s390x: CPU Topology
2023-05-05 9:34 UTC (4+ messages)
` [PATCH v20 06/21] s390x/cpu topology: interception of PTF instruction
[PATCH v4 0/7] Add EPYC-Genoa model and update previous EPYC Models
2023-05-05 8:31 UTC (4+ messages)
` [PATCH v4 4/7] target/i386: Add feature bits for CPUID_Fn80000021_EAX
[PATCH] vfio/pci: Static Resizable BAR capability
2023-05-05 8:29 UTC (2+ messages)
[PATCH] include/qemu/osdep.h: Bump _WIN32_WINNT to the Windows 8 API
2023-05-05 8:22 UTC (2+ messages)
[PATCH] scripts/coverity-scan: Add xtensa and openrisc components
2023-05-05 8:21 UTC (3+ messages)
[PATCH v4 00/10] COLO: improve build options
2023-05-05 8:21 UTC (8+ messages)
` [PATCH v4 10/10] migration: block incoming colo when capability is disabled
[PULL 0/6] Misc QGA patches
2023-05-04 14:41 UTC (2+ messages)
[PATCH 0/3] target/arm: disable-tcg and without-default-devices fixes
2023-05-05 8:18 UTC (7+ messages)
` [PATCH 1/3] target/arm: Use CONFIG_SEMIHOSTING instead of TCG for semihosting
[PATCH] hw: Fix format for comments
2023-05-05 7:23 UTC
[PATCH 0/9] QEMU file cleanups
2023-05-05 7:19 UTC (5+ messages)
` [PATCH 9/9] qemu-file: Account for rate_limit usage on qemu_fflush()
[PATCH v3 0/6] misc tweaks for kvm and the 64bit pci window
2023-05-05 7:11 UTC (7+ messages)
` [PATCH v3 1/6] better kvm detection
` [PATCH v3 2/6] detect physical address space size
` [PATCH v3 3/6] move 64bit pci window to end of address space
` [PATCH v3 4/6] be less conservative with the 64bit pci io window
` [PATCH v3 5/6] qemu: log reservations in fw_cfg e820 table
` [PATCH v3 6/6] check for e820 conflict
[PATCH v4 00/48] igb: Fix for DPDK
2023-05-05 6:46 UTC (3+ messages)
[RFC 0/7] vhost-vdpa: add support for iommufd
2023-05-05 6:29 UTC (3+ messages)
[PATCH] docs: vhost-user: VHOST_USER_GET_STATUS require reply
2023-05-05 5:39 UTC
[PATCH v3 0/5] virtio-gpu cleanups and obvious definitions
2023-05-05 4:56 UTC (2+ messages)
[PULL 00/45] loongarch-to-apply queue
2023-05-05 2:28 UTC (46+ messages)
` [PULL 01/45] target/loongarch: Add LSX data type VReg
` [PULL 02/45] target/loongarch: meson.build support build LSX
` [PULL 03/45] target/loongarch: Add CHECK_SXE maccro for check LSX enable
` [PULL 04/45] target/loongarch: Implement vadd/vsub
` [PULL 05/45] target/loongarch: Implement vaddi/vsubi
` [PULL 06/45] target/loongarch: Implement vneg
` [PULL 07/45] target/loongarch: Implement vsadd/vssub
` [PULL 08/45] target/loongarch: Implement vhaddw/vhsubw
` [PULL 09/45] target/loongarch: Implement vaddw/vsubw
` [PULL 10/45] target/loongarch: Implement vavg/vavgr
` [PULL 11/45] target/loongarch: Implement vabsd
` [PULL 12/45] target/loongarch: Implement vadda
` [PULL 13/45] target/loongarch: Implement vmax/vmin
` [PULL 14/45] target/loongarch: Implement vmul/vmuh/vmulw{ev/od}
` [PULL 15/45] target/loongarch: Implement vmadd/vmsub/vmaddw{ev/od}
` [PULL 16/45] target/loongarch: Implement vdiv/vmod
` [PULL 17/45] target/loongarch: Implement vsat
` [PULL 18/45] target/loongarch: Implement vexth
` [PULL 19/45] target/loongarch: Implement vsigncov
` [PULL 20/45] target/loongarch: Implement vmskltz/vmskgez/vmsknz
` [PULL 21/45] target/loongarch: Implement LSX logic instructions
` [PULL 22/45] target/loongarch: Implement vsll vsrl vsra vrotr
` [PULL 23/45] target/loongarch: Implement vsllwil vextl
` [PULL 24/45] target/loongarch: Implement vsrlr vsrar
` [PULL 25/45] target/loongarch: Implement vsrln vsran
` [PULL 26/45] target/loongarch: Implement vsrlrn vsrarn
` [PULL 27/45] target/loongarch: Implement vssrln vssran
` [PULL 28/45] target/loongarch: Implement vssrlrn vssrarn
` [PULL 29/45] target/loongarch: Implement vclo vclz
` [PULL 30/45] target/loongarch: Implement vpcnt
` [PULL 31/45] target/loongarch: Implement vbitclr vbitset vbitrev
` [PULL 32/45] target/loongarch: Implement vfrstp
` [PULL 33/45] target/loongarch: Implement LSX fpu arith instructions
` [PULL 34/45] target/loongarch: Implement LSX fpu fcvt instructions
` [PULL 35/45] target/loongarch: Implement vseq vsle vslt
` [PULL 36/45] target/loongarch: Implement vfcmp
` [PULL 37/45] target/loongarch: Implement vbitsel vset
` [PULL 38/45] target/loongarch: Implement vinsgr2vr vpickve2gr vreplgr2vr
` [PULL 39/45] target/loongarch: Implement vreplve vpack vpick
` [PULL 40/45] target/loongarch: Implement vilvl vilvh vextrins vshuf
` [PULL 41/45] target/loongarch: Implement vld vst
` [PULL 42/45] target/loongarch: Implement vldi
` [PULL 43/45] target/loongarch: Use {set/get}_gpr replace to cpu_fpr
` [PULL 44/45] target/loongarch: CPUCFG support LSX
` [PULL 45/45] hw/intc: don't use target_ulong for LoongArch ipi
[PATCH v3 0/3] target/riscv: implement query-cpu-definitions
2023-05-05 1:59 UTC (4+ messages)
[PULL 00/89] riscv-to-apply queue
2023-05-05 1:08 UTC (92+ messages)
` [PULL 01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig
` [PULL 02/89] target/riscv: Fix priv version dependency for vector and zfh
` [PULL 03/89] target/riscv: Simplify getting RISCVCPU pointer from env
` [PULL 04/89] target/riscv: Simplify type conversion for CPURISCVState
` [PULL 05/89] target/riscv: Simplify arguments for riscv_csrrw_check
` [PULL 06/89] target/riscv: refactor Zicond support
` [PULL 07/89] target/riscv: redirect XVentanaCondOps to use the Zicond functions
` [PULL 08/89] target/riscv: fix invalid riscv, event-to-mhpmcounters entry
` [PULL 09/89] target/riscv: add cfg properties for Zc* extension
` [PULL 10/89] target/riscv: add support for Zca extension
` [PULL 11/89] target/riscv: add support for Zcf extension
` [PULL 12/89] target/riscv: add support for Zcd extension
` [PULL 13/89] target/riscv: add support for Zcb extension
` [PULL 14/89] target/riscv: add support for Zcmp extension
` [PULL 15/89] target/riscv: add support for Zcmt extension
` [PULL 16/89] target/riscv: expose properties for Zc* extension
` [PULL 17/89] disas/riscv.c: add disasm support for Zc*
` [PULL 18/89] target/riscv: Add support for Zce
` [PULL 19/89] target/riscv: Fix itrigger when icount is used
` [PULL 20/89] target/riscv: Remove redundant call to riscv_cpu_virt_enabled
` [PULL 21/89] target/riscv: Remove redundant check on RVH
` [PULL 22/89] target/riscv: Remove check on RVH for riscv_cpu_virt_enabled
` [PULL 23/89] target/riscv: Remove check on RVH for riscv_cpu_set_virt_enabled
` [PULL 24/89] target/riscv: Convert env->virt to a bool env->virt_enabled
` [PULL 25/89] target/riscv: Remove redundant parentheses
` [PULL 26/89] target/riscv: Fix addr type for get_physical_address
` [PULL 27/89] target/riscv: Set opcode to env->bins for illegal/virtual instruction fault
` [PULL 28/89] target/riscv: Remove riscv_cpu_virt_enabled()
` [PULL 29/89] target/riscv: Fix format for indentation
` [PULL 30/89] target/riscv: Fix format for comments
` [PULL 31/89] target/riscv: Fix lines with over 80 characters
` [PULL 32/89] hw/riscv: Add signature dump function for spike to run ACT tests
` [PULL 33/89] target/riscv: sync env->misa_ext* with cpu->cfg in realize()
` [PULL 34/89] target/riscv: remove MISA properties from isa_edata_arr[]
` [PULL 35/89] target/riscv/cpu.c: remove 'multi_letter' from isa_ext_data
` [PULL 36/89] target/riscv: introduce riscv_cpu_add_misa_properties()
` [PULL 37/89] target/riscv: remove cpu->cfg.ext_a
` [PULL 38/89] target/riscv: remove cpu->cfg.ext_c
` [PULL 39/89] target/riscv: remove cpu->cfg.ext_d
` [PULL 40/89] target/riscv: remove cpu->cfg.ext_f
` [PULL 41/89] target/riscv: remove cpu->cfg.ext_i
` [PULL 42/89] target/riscv: remove cpu->cfg.ext_e
` [PULL 43/89] target/riscv: remove cpu->cfg.ext_m
` [PULL 44/89] target/riscv: remove cpu->cfg.ext_s
` [PULL 45/89] target/riscv: remove cpu->cfg.ext_u
` [PULL 46/89] target/riscv: remove cpu->cfg.ext_h
` [PULL 47/89] target/riscv: remove cpu->cfg.ext_j
` [PULL 48/89] target/riscv: remove cpu->cfg.ext_v
` [PULL 49/89] target/riscv: remove riscv_cpu_sync_misa_cfg()
` [PULL 50/89] target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init()
` [PULL 51/89] target/riscv: add RVG and remove cpu->cfg.ext_g
` [PULL 52/89] target/riscv/cpu.c: redesign register_cpu_props()
` [PULL 53/89] target/riscv: Fix the mstatus.MPP value after executing MRET
` [PULL 54/89] target/riscv: Use PRV_RESERVED instead of PRV_H
` [PULL 55/89] target/riscv: Legalize MPP value in write_mstatus
` [PULL 56/89] target/riscv: Use check for relationship between Zdinx/Zhinx{min} and Zfinx
` [PULL 57/89] target/riscv: fix H extension TVM trap
` [PULL 58/89] target/riscv: Extract virt enabled state from tb flags
` [PULL 59/89] target/riscv: Add a general status enum for extensions
` [PULL 60/89] target/riscv: Encode the FS and VS on a normal way for tb flags
` [PULL 61/89] target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags
` [PULL 62/89] target/riscv: Add a tb flags field for vstart
` [PULL 63/89] target/riscv: Separate priv from mmu_idx
` [PULL 64/89] target/riscv: Reduce overhead of MSTATUS_SUM change
` [PULL 65/89] target/riscv: Use cpu_ld*_code_mmu for HLVX
` [PULL 66/89] target/riscv: Handle HLV, HSV via helpers
` [PULL 67/89] target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT
` [PULL 68/89] target/riscv: Introduce mmuidx_sum
` [PULL 69/89] target/riscv: Introduce mmuidx_priv
` [PULL 70/89] target/riscv: Introduce mmuidx_2stage
` [PULL 71/89] target/riscv: Move hstatus.spvp check to check_access_hlsv
` [PULL 72/89] target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index
` [PULL 73/89] target/riscv: Check SUM in the correct register
` [PULL 74/89] target/riscv: Hoist second stage mode change to callers
` [PULL 75/89] target/riscv: Hoist pbmte and hade out of the level loop
` [PULL 76/89] target/riscv: Move leaf pte processing out of "
` [PULL 77/89] target/riscv: Suppress pte update with is_debug
` [PULL 78/89] target/riscv: Don't modify SUM "
` [PULL 79/89] target/riscv: Merge checks for reserved pte flags
` [PULL 80/89] target/riscv: Reorg access check in get_physical_address
` [PULL 81/89] target/riscv: Reorg sum "
` [PULL 82/89] hw/intc/riscv_aplic: Zero init APLIC internal state
` [PULL 83/89] target/riscv: add CPU QOM header
` [PULL 84/89] target/riscv: add query-cpy-definitions support
` [PULL 85/89] target/riscv: add TYPE_RISCV_DYNAMIC_CPU
` [PULL 86/89] target/riscv: Restore the predicate() NULL check behavior
` [PULL 87/89] target/riscv: Fix Guest Physical Address Translation
` [PULL 88/89] riscv: Make sure an exception is raised if a pte is malformed
` [PULL 89/89] target/riscv: add Ventana's Veyron V1 CPU
[PULL 00/16] Migration 20230505 patches
2023-05-05 0:48 UTC (6+ messages)
` [PULL 07/16] migration/rdma: simplify ram_control_load_hook()
` [PULL 08/16] migration/rdma: We can calculate the rioc from the QEMUFile
` [PULL 10/16] migration/rdma: Check for postcopy sooner
` [PULL 12/16] migration: qemu_file_total_transferred() function is monotonic
` [PULL 16/16] qemu-file: Make ram_control_save_page() use accessors for rate_limit
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