messages from 2025-04-04 14:37:21 to 2025-04-06 07:07:07 UTC [more...]
[PATCH 10.1 v3 00/27] target/riscv: SATP mode and CPU definition overhaul
2025-04-06 7:02 UTC (24+ messages)
` [PATCH 01/27] hw/riscv: acpi: only create RHCT MMU entry for supported types
` [PATCH 02/27] target/riscv: assert argument to set_satp_mode_max_supported is valid
` [PATCH 03/27] target/riscv: cpu: store max SATP mode as a single integer
` [PATCH 04/27] target/riscv: update max_satp_mode based on QOM properties
` [PATCH 05/27] target/riscv: remove supported from RISCVSATPMap
` [PATCH 06/27] target/riscv: move satp_mode.{map, init} out of CPUConfig
` [PATCH 07/27] target/riscv: introduce RISCVCPUDef
` [PATCH 09/27] target/riscv: merge riscv_cpu_class_init with the class_base function
` [PATCH 11/27] target/riscv: include default value in cpu_cfg_fields.h.inc
` [PATCH 12/27] target/riscv: do not make RISCVCPUConfig fields conditional
` [PATCH 13/27] target/riscv: add more RISCVCPUDef fields
` [PATCH 14/27] target/riscv: convert abstract CPU classes to RISCVCPUDef
` [PATCH 15/27] target/riscv: convert profile CPU models "
` [PATCH 16/27] target/riscv: convert bare "
` [PATCH 17/27] target/riscv: convert dynamic "
` [PATCH 18/27] target/riscv: convert SiFive E "
` [PATCH 19/27] target/riscv: convert ibex "
` [PATCH 20/27] target/riscv: convert SiFive U "
` [PATCH 22/27] target/riscv: generalize custom CSR functionality
` [PATCH 24/27] target/riscv: convert TT Ascalon to RISCVCPUDef
` [PATCH 25/27] target/riscv: convert Ventana V1 "
` [PATCH 26/27] target/riscv: convert Xiangshan Nanhu "
` [PATCH 27/27] target/riscv: remove .instance_post_init
[PATCH 0/2] Add property to support writing ERSTBA in high-low order
2025-04-06 1:31 UTC (9+ messages)
` [PATCH 1/2] hw: usb: xhci: "
` [PATCH 2/2] hw/usb/hcd-dwc3: Set erstba-hi-lo property
[PATCH v5] block/file-posix.c: Use pwritev2() with RWF_DSYNC for FUA
2025-04-05 23:52 UTC
[PATCH-for-10.0 0/3] More imx8mp-evk improvements
2025-04-05 21:49 UTC (4+ messages)
` [PATCH-for-10.0 1/3] tests/functional: Add test for imx8mp-evk board with USDHC coverage
` [PATCH-for-10.0 2/3] hw/arm/imx8mp-evk: Remove unimplemented cpu-idle-states properties from devicetree
` [PATCH-for-10.0 3/3] hw/arm/imx8mp-evk: Remove unimplemented nxp, imx8mp-fspi node "
[PATCH v3] hw/arm/virt: Allow additions to the generated device tree
2025-04-05 19:13 UTC
Can I contribute Vitastor block driver? Or maybe introduce a QAPI plugin system?
2025-04-05 16:37 UTC (3+ messages)
[PATCH-for-10.1 0/9] target/arm: Remove some TARGET_AARCH64 uses (MTE & gdbstub)
2025-04-05 16:33 UTC (18+ messages)
` [PATCH-for-10.1 1/9] target/arm: Remove uses of TARGET_AARCH64 in arch_dump.c
` [PATCH-for-10.1 2/9] target/arm: Remove use of TARGET_AARCH64 in dump.c
` [PATCH-for-10.1 3/9] target/arm: Remove use of TARGET_AARCH64 in arm_cpu_initfn()
` [PATCH-for-10.1 4/9] target/arm/mte: Include missing headers for GETPC()
` [PATCH-for-10.1 5/9] target/arm/mte: Reduce address_with_allocation_tag() scope
` [PATCH-for-10.1 6/9] target/arm/mte: Rename 'mte_helper.h' as generic 'mte.h'
` [PATCH-for-10.1 7/9] target/arm/mte: Restrict MTE declarations
` [PATCH-for-10.1 8/9] linux-user/arm: Implement MTE stubs for 32-bit user emulation
` [PATCH-for-10.1 9/9] target/arm: Build Aarch64 gdbstub helpers indistinctly
[PATCH v2 0/3] tcg: Convert TARGET_HAS_PRECISE_SMC to TCGCPUOps.precise_smc
2025-04-05 16:17 UTC (8+ messages)
` [PATCH v2 1/3] accel/tcg: Add CPUState argument to page_unprotect
` [PATCH v2 2/3] accel/tcg: Add CPUState argument to tb_invalidate_phys_page_unwind
` [PATCH v2 3/3] accel/tcg: Convert TARGET_HAS_PRECISE_SMC to TCGCPUOps.precise_smc
[PATCH-for-10.1 v4 00/16] tcg: philmd's queue
2025-04-05 16:13 UTC (17+ messages)
` [PATCH-for-10.1 v4 01/16] target/riscv: Remove AccelCPUClass::cpu_class_init need
` [PATCH-for-10.1 v4 02/16] target/i386: "
` [PATCH-for-10.1 v4 03/16] accel: Remove AccelCPUClass::cpu_class_init() callback
` [PATCH-for-10.1 v4 04/16] target/hexagon: Add memory order definition
` [PATCH-for-10.1 v4 05/16] tcg: Always define TCG_GUEST_DEFAULT_MO
` [PATCH-for-10.1 v4 06/16] tcg: Simplify tcg_req_mo() macro
` [PATCH-for-10.1 v4 07/16] tcg: Define guest_default_memory_order in TCGCPUOps
` [PATCH-for-10.1 v4 08/16] tcg: Remove use of TCG_GUEST_DEFAULT_MO in tb_gen_code()
` [PATCH-for-10.1 v4 09/16] tcg: Propagate CPUState argument to cpu_req_mo()
` [PATCH-for-10.1 v4 10/16] tcg: Have tcg_req_mo() use TCGCPUOps::guest_default_memory_order
` [PATCH-for-10.1 v4 11/16] tcg: Remove the TCG_GUEST_DEFAULT_MO definition globally
` [PATCH-for-10.1 v4 12/16] tcg: Move cpu_req_mo() macro to target-agnostic 'backend-ldst.h'
` [PATCH-for-10.1 v4 13/16] tcg: Move qemu_tcg_mttcg_enabled() to 'system/tcg.h'
` [PATCH-for-10.1 v4 14/16] tcg: Convert TCGState::mttcg_enabled to TriState
` [PATCH-for-10.1 v4 15/16] tcg: Factor mttcg_init() out
` [PATCH-for-10.1 v4 16/16] tcg: Convert TARGET_SUPPORTS_MTTCG to TCGCPUOps::mttcg_supported field
[PATCH-for-10.1 0/2] tcg: Convert TARGET_HAS_PRECISE_SMC to TCGCPUOps::has_precise_smc field
2025-04-05 15:57 UTC (4+ messages)
` [PATCH-for-10.1 1/2] tcg: Introduce and use target_has_precise_smc() runtime helper
` [PATCH-for-10.1 2/2] tcg: Convert TARGET_HAS_PRECISE_SMC to TCGCPUOps::has_precise_smc field
[RFC PATCH-for-10.1 00/39] single-binary: Make hw/arm/ common
2025-04-05 14:43 UTC (33+ messages)
` [RFC PATCH-for-10.1 01/39] target/arm: Implement per-binary TargetInfo structures
` [RFC PATCH-for-10.1 03/39] target/arm: Filter CPU types for binary
` [RFC PATCH-for-10.1 11/39] hw/arm: Use full "target/arm/cpu.h" path to include target's "cpu.h"
` [RFC PATCH-for-10.1 20/39] target/arm: Extract PSCI definitions to 'psci.h'
` [RFC PATCH-for-10.1 27/39] system/hvf: Expose hvf_enabled() to common code
` [RFC PATCH-for-10.1 28/39] exec: Do not poison hardware accelerators
` [RFC PATCH-for-10.1 35/39] hw/arm/virt: Replace TARGET_AARCH64 -> target_long_bits()
` [RFC PATCH-for-10.1 38/39] hw/arm: Move xen files to arm_common_ss[]
[PATCH v5 00/46] x86: Improve operation under QEMU
2025-04-05 14:31 UTC (2+ messages)
Question about memory trace with execlog plugin
2025-04-05 14:25 UTC
[PATCH-for-10.1 v3 00/19] tcg: philmd's queue
2025-04-05 14:14 UTC (6+ messages)
` [PATCH-for-10.1 v3 14/19] tcg: Remove the TCG_GUEST_DEFAULT_MO definition globally
` [PATCH-for-10.1 v3 19/19] tcg: Convert TARGET_SUPPORTS_MTTCG to TCGCPUOps::mttcg_supported field
[PATCH preview 0/3] rust: update build system for Meson 1.8.0
2025-04-05 12:23 UTC (5+ messages)
` [PATCH 1/3] rust: use "objects" for Rust executables as well
` [PATCH 2/3] rust: add qemu-api doctests to "meson test"
` [PATCH 3/3] rust: cell: remove support for running doctests with "cargo test --doc"
` [PATCH 4/3] rust: use native Meson support for clippy and rustdoc
[PATCH v2 00/12] Fix RVV encoding corner cases
2025-04-05 9:21 UTC (25+ messages)
` [PATCH v2 01/12] target/riscv: rvv: Source vector registers cannot overlap mask register
` [PATCH v2 02/12] target/riscv: rvv: Add CHECK arg to GEN_OPFVF_WIDEN_TRANS
` [PATCH v2 03/12] target/riscv: Add vext_check_input_eew to check mismatched input EEWs encoding constraint
` [PATCH v2 04/12] target/riscv: rvv: Apply vext_check_input_eew to vector register gather instructions
` [PATCH v2 05/12] target/riscv: rvv: Apply vext_check_input_eew to OPIVI/OPIVX/OPFVF(vext_check_ss) instructions
` [PATCH v2 06/12] target/riscv: rvv: Apply vext_check_input_eew to OPIVV/OPFVV(vext_check_sss) instructions
` [PATCH v2 07/12] target/riscv: rvv: Apply vext_check_input_eew to vector slide instructions(OPIVI/OPIVX)
` [PATCH v2 08/12] target/riscv: rvv: Apply vext_check_input_eew to vector integer extension instructions(OPMVV)
` [PATCH v2 09/12] target/riscv: rvv: Apply vext_check_input_eew to vector widen instructions(OPMVV/OPMVX/etc.)
` [PATCH v2 10/12] target/riscv: rvv: Apply vext_check_input_eew to vector narrow instructions
` [PATCH v2 11/12] target/riscv: rvv: Apply vext_check_input_eew to vector indexed load/store instructions
` [PATCH v2 12/12] target/riscv: Fix the rvv reserved encoding of unmasked instructions
[PATCH] virtio-net: Copy all for dhclient workaround
2025-04-05 8:04 UTC
[PATCH] [for-10.1] qapi/block-core: derpecate some block-job- APIs
2025-04-05 7:13 UTC (6+ messages)
[PATCH rfcv2 00/20] intel_iommu: Enable stage-1 translation for passthrough device
2025-04-05 3:01 UTC (2+ messages)
[PATCH v2] ppc/vof: Make nextprop behave more like Open Firmware
2025-04-05 0:09 UTC (3+ messages)
[PATCH 0/2] hw/riscv/virt.c: change default CPU to 'max'
2025-04-04 23:01 UTC (4+ messages)
` [PATCH 1/2] target/riscv/tcg: make 'max' cpu rva23s64 compliant
` [PATCH 2/2] hw/riscv/virt.c: change default CPU to 'max'
[PATCH 0/4] migration: savevm testing
2025-04-04 20:26 UTC (5+ messages)
` [PATCH 1/4] migration/savevm: Add a compatibility check for capabilities
[PATCH v2 0/2] derpecate some block-job- APIs
2025-04-04 19:31 UTC (3+ messages)
` [PATCH v2 1/2] qapi: synchronize jobs and block-jobs documentation
` [PATCH v2 2/2] qapi/block-core: derpecate some block-job- APIs
[PATCH] hw/ipmi: Move vmsd registration to device class
2025-04-04 18:17 UTC (3+ messages)
[RFC PATCH-for-10.1 00/19] qemu: Introduce TargetInfo API (for single binary)
2025-04-04 18:11 UTC (47+ messages)
` [RFC PATCH-for-10.1 01/19] qemu: Introduce TargetInfo API in 'target_info.h'
` [RFC PATCH-for-10.1 02/19] qemu: Convert target_name() to TargetInfo API
` [RFC PATCH-for-10.1 03/19] qemu: Factor target_system_arch() out
` [RFC PATCH-for-10.1 04/19] qemu: Convert target_words_bigendian() to TargetInfo API
` [RFC PATCH-for-10.1 05/19] qemu: Introduce target_long_bits()
` [RFC PATCH-for-10.1 06/19] target/tricore: Replace TARGET_LONG_BITS -> target_long_bits()
` [RFC PATCH-for-10.1 07/19] target/hppa: "
` [RFC PATCH-for-10.1 08/19] target/riscv: "
` [RFC PATCH-for-10.1 09/19] qemu: Introduce target_cpu_type()
` [RFC PATCH-for-10.1 10/19] cpus: Replace CPU_RESOLVING_TYPE -> target_cpu_type()
` [RFC PATCH-for-10.1 11/19] accel/tcg: "
` [RFC PATCH-for-10.1 12/19] cpus: Move target-agnostic methods out of cpu-target.c
` [RFC PATCH-for-10.1 13/19] accel: Replace CPU_RESOLVING_TYPE -> target_cpu_type()
` [RFC PATCH-for-10.1 14/19] accel: Implement accel_init_ops_interfaces() for both system/user mode
` [RFC PATCH-for-10.1 15/19] accel: Include missing 'qemu/accel.h' header in accel-internal.h
` [RFC PATCH-for-10.1 16/19] accel: Make AccelCPUClass structure target-agnostic
` [RFC PATCH-for-10.1 17/19] accel: Move target-agnostic code from accel-target.c -> accel-common.c
` [RFC PATCH-for-10.1 18/19] qemu: Prepare per-binary QOM filter via TYPE_BINARY_PREFIX
` [RFC PATCH-for-10.1 19/19] system/vl: Filter machine list for binary using machine_binary_filter()
[PATCH 0/9] hw/nvme: refactor/cleanup
2025-04-04 17:52 UTC (2+ messages)
` hw/nvme: Issue with multiple controllers behind a subsystem
[PATCH v8 00/28] vfio-user client
2025-04-04 17:21 UTC (26+ messages)
` [PATCH v8 03/28] vfio/container: support VFIO_DMA_UNMAP_FLAG_ALL
` [PATCH v8 05/28] vfio: add vfio_prepare_device()
` [PATCH v8 08/28] vfio: add region cache
` [PATCH v8 09/28] vfio: split out VFIOKernelPCIDevice
` [PATCH v8 10/28] vfio: add device IO ops vector
[PULL 0/1] Migration patches for 2025-04-01
2025-04-04 17:07 UTC (2+ messages)
[PULL 0/6] tcg patch queue for 10.0-rc3
2025-04-04 17:08 UTC (2+ messages)
[PULL -rce 0/1] NBD patches for 2025-04-03
2025-04-04 17:08 UTC (2+ messages)
[PULL 0/2] virtio,pc: fixes
2025-04-04 17:07 UTC (2+ messages)
[PATCH v4] block/file-posix.c: Use pwritev2() with RWF_DSYNC for FUA
2025-04-04 15:05 UTC (2+ messages)
[PATCH] Revert "virtio-net: Copy received header to buffer"
2025-04-04 15:18 UTC
[PATCH] smbios: Fix buffer overrun when using path= option
2025-04-04 15:06 UTC (6+ messages)
[PATCH] hw/ipmi: Allow multiple BMC instances
2025-04-04 15:25 UTC (5+ messages)
[PATCH 0/6] misc hexagon patches
2025-04-04 15:20 UTC (4+ messages)
` [PATCH 6/6] target/hexagon: Add memory order definition
[PATCH] docs/cxl: Add serial number for persistent-memdev
2025-04-04 15:02 UTC (9+ messages)
[PATCH] hw/9pfs: add cleanup operation for 9p-synth
2025-04-04 14:38 UTC (3+ messages)
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