messages from 2025-04-25 15:33:03 to 2025-04-25 22:17:38 UTC [more...]
[PULL 000/159] tcg patch queue
2025-04-25 21:54 UTC (88+ messages)
` [PULL 001/159] tcg/loongarch64: Fix vec_val computation in tcg_target_const_match
` [PULL 002/159] tcg/loongarch64: Improve constraints for TCG_CT_CONST_VCMP
` [PULL 003/159] tcg/optimize: Introduce opt_insert_{before,after}
` [PULL 004/159] tcg: Add TCGType to tcg_op_insert_{after,before}
` [PULL 005/159] tcg: Add all_outop[]
` [PULL 006/159] tcg: Use extract2 for cross-word 64-bit extract on 32-bit host
` [PULL 007/159] tcg: Remove INDEX_op_ext{8,16,32}*
` [PULL 008/159] tcg: Merge INDEX_op_mov_{i32,i64}
` [PULL 009/159] tcg: Convert add to TCGOutOpBinary
` [PULL 010/159] tcg: Merge INDEX_op_add_{i32,i64}
` [PULL 011/159] tcg: Convert and to TCGOutOpBinary
` [PULL 012/159] tcg: Merge INDEX_op_and_{i32,i64}
` [PULL 013/159] tcg/optimize: Fold andc with immediate to and
` [PULL 014/159] tcg/optimize: Emit add r, r, -1 in fold_setcond_tst_pow2
` [PULL 015/159] tcg: Convert andc to TCGOutOpBinary
` [PULL 017/159] tcg: Convert or "
` [PULL 018/159] tcg: Merge INDEX_op_or_{i32,i64}
` [PULL 019/159] tcg/optimize: Fold orc with immediate to or
` [PULL 020/159] tcg: Convert orc to TCGOutOpBinary
` [PULL 023/159] tcg: Merge INDEX_op_xor_{i32,i64}
` [PULL 024/159] tcg/optimize: Fold eqv with immediate to xor
` [PULL 025/159] tcg: Convert eqv to TCGOutOpBinary
` [PULL 026/159] tcg: Merge INDEX_op_eqv_{i32,i64}
` [PULL 027/159] tcg: Convert nand to TCGOutOpBinary
` [PULL 029/159] tcg/loongarch64: Do not accept constant argument to nor
` [PULL 030/159] tcg: Convert nor to TCGOutOpBinary
` [PULL 031/159] tcg: Merge INDEX_op_nor_{i32,i64}
` [PULL 032/159] tcg/arm: Fix constraints for sub
` [PULL 034/159] tcg: Merge INDEX_op_sub_{i32,i64}
` [PULL 035/159] tcg: Convert neg to TCGOutOpUnary
` [PULL 036/159] tcg: Merge INDEX_op_neg_{i32,i64}
` [PULL 037/159] tcg: Convert not to TCGOutOpUnary
` [PULL 041/159] tcg: Convert muluh to TCGOutOpBinary
` [PULL 042/159] tcg: Merge INDEX_op_muluh_{i32,i64}
` [PULL 043/159] tcg: Convert mulsh to TCGOutOpBinary
` [PULL 045/159] tcg: Convert div "
` [PULL 046/159] tcg: Merge INDEX_op_div_{i32,i64}
` [PULL 047/159] tcg: Convert divu to TCGOutOpBinary
` [PULL 048/159] tcg: Merge INDEX_op_divu_{i32,i64}
` [PULL 049/159] tcg: Convert div2 to TCGOutOpDivRem
` [PULL 050/159] tcg: Merge INDEX_op_div2_{i32,i64}
` [PULL 051/159] tcg: Convert divu2 to TCGOutOpDivRem
` [PULL 052/159] tcg: Merge INDEX_op_divu2_{i32,i64}
` [PULL 053/159] tcg: Convert rem to TCGOutOpBinary
` [PULL 055/159] tcg: Convert remu "
` [PULL 056/159] tcg: Merge INDEX_op_remu_{i32,i64}
` [PULL 057/159] tcg: Convert shl to TCGOutOpBinary
` [PULL 058/159] tcg: Merge INDEX_op_shl_{i32,i64}
` [PULL 059/159] tcg: Convert shr to TCGOutOpBinary
` [PULL 061/159] tcg: Convert sar "
` [PULL 063/159] tcg: Do not require both rotr and rotl from the backend
` [PULL 064/159] tcg: Convert rotl, rotr to TCGOutOpBinary
` [PULL 065/159] tcg: Merge INDEX_op_rot{l,r}_{i32,i64}
` [PULL 066/159] tcg: Convert clz to TCGOutOpBinary
` [PULL 067/159] tcg: Merge INDEX_op_clz_{i32,i64}
` [PULL 068/159] tcg: Convert ctz to TCGOutOpBinary
` [PULL 071/159] tcg: Merge INDEX_op_ctpop_{i32,i64}
` [PULL 072/159] tcg: Convert muls2 to TCGOutOpMul2
` [PULL 074/159] tcg: Convert mulu2 "
` [PULL 076/159] tcg/loongarch64: Support negsetcond
` [PULL 077/159] tcg/mips: "
` [PULL 078/159] tcg/tci: "
` [PULL 079/159] tcg: Remove TCG_TARGET_HAS_negsetcond_{i32,i64}
` [PULL 082/159] tcg: Convert brcond to TCGOutOpBrcond
` [PULL 083/159] tcg: Merge INDEX_op_brcond_{i32,i64}
` [PULL 084/159] tcg: Convert movcond to TCGOutOpMovcond
` [PULL 088/159] tcg/ppc: Expand arguments to tcg_out_cmp2
` [PULL 092/159] tcg: Merge INDEX_op_bswap16_{i32,i64}
` [PULL 095/159] tcg: Convert bswap64 to TCGOutOpUnary
` [PULL 096/159] tcg: Rename INDEX_op_bswap64_i64 to INDEX_op_bswap64
` [PULL 097/159] tcg: Convert extract to TCGOutOpExtract
` [PULL 099/159] tcg: Convert sextract "
` [PULL 105/159] tcg: Convert deposit to TCGOutOpDeposit
` [PULL 106/159] tcg/aarch64: Improve deposit
` [PULL 107/159] tcg: Merge INDEX_op_deposit_{i32,i64}
` [PULL 109/159] tcg: Merge INDEX_op_extract2_{i32,i64}
` [PULL 111/159] tcg: Expand fallback sub2 with 32-bit operations
` [PULL 112/159] tcg: Do not default add2/sub2_i32 for 32-bit hosts
` [PULL 113/159] tcg/mips: Drop support for add2/sub2
` [PULL 115/159] tcg: Move i into each for loop in liveness_pass_1
` [PULL 118/159] tcg: Add TCGOutOp structures for add/sub carry opcodes
` [PULL 123/159] tcg/i386: Honor carry_live in tcg_out_movi
` [PULL 127/159] target/arm: Use tcg_gen_addcio_* for ADCS
` [PULL 128/159] target/hppa: Use tcg_gen_addcio_i64
` [PULL 138/159] tcg/ppc: Implement add/sub carry opcodes
` [PULL 146/159] tcg: Remove add2/sub2 opcodes
` [PULL 156/159] tcg: Merge INDEX_op_{ld,st}_{i32,i64,i128}
[PATCH alternate 0/2] target/riscv: Fix write_misa vs aligned next_pc
2025-04-25 22:02 UTC (4+ messages)
` [PATCH alternate 1/2] target/riscv: Update pc before csrw, csrrw
` [PATCH alternate 2/2] target/riscv: Fix write_misa vs aligned next_pc
[PATCH v5 00/10] target/i386/kvm/pmu: PMU Enhancement, Bugfix and Cleanup
2025-04-25 21:30 UTC (11+ messages)
` [PATCH v5 01/10] target/i386: disable PerfMonV2 when PERFCORE unavailable
` [PATCH v5 02/10] target/i386: disable PERFCORE when "-pmu" is configured
` [PATCH v5 03/10] kvm: Introduce kvm_arch_pre_create_vcpu()
` [PATCH v5 04/10] target/i386/kvm: set KVM_PMU_CAP_DISABLE if "-pmu" is configured
` [PATCH v5 05/10] target/i386/kvm: extract unrelated code out of kvm_x86_build_cpuid()
` [PATCH v5 06/10] target/i386/kvm: rename architectural PMU variables
` [PATCH v5 07/10] target/i386/kvm: query kvm.enable_pmu parameter
` [PATCH v5 08/10] target/i386/kvm: reset AMD PMU registers during VM reset
` [PATCH v5 09/10] target/i386/kvm: support perfmon-v2 for reset
` [PATCH v5 10/10] target/i386/kvm: don't stop Intel PMU counters
[RFC PATCH 0/3] single-binary: make QAPI generated files common
2025-04-25 21:13 UTC (6+ messages)
[RFC PATCH v5 00/21] single-binary: Make hw/arm/ common
2025-04-25 20:36 UTC (8+ messages)
` [RFC PATCH v5 08/21] hw/arm: Add DEFINE_MACHINE_[ARM_]AARCH64() macros
[PATCH 0/2] tcg/sparc64: Implement CTPOP
2025-04-25 20:00 UTC (3+ messages)
` [PATCH 1/2] tcg/sparc64: Unexport use_vis3_instructions
` [PATCH 2/2] tcg/sparc64: Implement CTPOP
[PATCH 00/21] Hi,
2025-04-25 19:59 UTC (19+ messages)
` [PATCH 03/21] hw/dma/zynq-devcfg: Handle bitstream loading via DMA to 0xffffffff
` [PATCH 04/21] hw/arm/zynq-devcfg: Prevent unintended unlock during initialization
` [PATCH 05/21] hw/dma/zynq: Notify devcfg on FPGA reset via SLCR control
` [PATCH 06/21] hw/dma/zynq-devcfg: Simulate dummy PL reset
` [PATCH 07/21] hw/dma/zynq-devcfg: Indicate power-up status of PL
` [PATCH 08/21] hw/dma/zynq-devcfg: Fix register memory
` [PATCH 09/21] hw/misc: Add dummy ZYNQ DDR controller
` [PATCH 10/21] hw/misc/zynq_slcr: Add logic for DCI configuration
` [PATCH 00/21] hw/arm: add CX7200 board emulation
[PATCH 00/15] accel/tcg: Compile tb-maint.c twice
2025-04-25 19:46 UTC (31+ messages)
` [PATCH 01/15] accel/tcg: Add CPUState argument to page_unprotect
` [PATCH 02/15] accel/tcg: Add CPUState argument to tb_invalidate_phys_page_unwind
` [PATCH 03/15] accel/tcg: Add CPUState arg to tb_invalidate_phys_page_range__locked
` [PATCH 04/15] accel/tcg: Merge tb_invalidate_phys_range{__locked}
` [PATCH 05/15] accel/tcg: Add CPUState arg to tb_invalidate_phys_range
` [PATCH 06/15] accel/tcg: Add CPUState arg to tb_invalidate_phys_range_fast
` [PATCH 07/15] accel/tcg: Convert TARGET_HAS_PRECISE_SMC to TCGCPUOps.precise_smc
` [PATCH 08/15] accel/tcg: Simplify CPU_TLB_DYN_MAX_BITS
` [PATCH 09/15] accel/tcg: Simplify L1_MAP_ADDR_SPACE_BITS
` [PATCH 10/15] accel/tcg: Merge internal-target.h into internal-common.h
` [PATCH 11/15] accel/tcg: Reduce scope of tb_phys_invalidate, tb_set_jmp_target
` [PATCH 12/15] accel/tcg: Use vaddr for walk_memory_regions callback
` [PATCH 13/15] accel/tcg: Use vaddr in user/page-protection.h
` [PATCH 14/15] include/exec: Move tb_invalidate_phys_range to translation-block.h
` [PATCH 15/15] accel/tcg: Compile tb-maint.c twice
[PATCH v1 0/1] xen: mapcache: grants: Fix mixup betwen ro and rw mappings
2025-04-25 19:26 UTC (3+ messages)
` [PATCH v1 1/1] xen: mapcache: Split mapcache_grants by ro and rw
[PATCH] vfio: Register/unregister container for CPR only once for each container
2025-04-25 19:14 UTC (3+ messages)
[PATCH 0/9] riscv: Add support for MIPS P8700 CPU
2025-04-25 18:24 UTC (3+ messages)
` [PATCH 5/9] target/riscv: Add mips.ccmov instruction
[PULL 0/4] Block layer patches
2025-04-25 17:52 UTC (5+ messages)
` [PULL 1/4] file-posix: probe discard alignment on Linux block devices
` [PULL 2/4] block/io: skip head/tail requests on EINVAL
` [PULL 3/4] block: Remove unused callback function *bdrv_aio_pdiscard
` [PULL 4/4] qemu-img: improve queue depth validation in img_bench
[PATCH] target/i386/hvf: Include missing 'exec/target_page.h' header
2025-04-25 17:51 UTC (2+ messages)
[PATCH 000/147] single-binary patch queue
2025-04-25 17:35 UTC (3+ messages)
` [PATCH 066/147] include/exec: Move TLB_MMIO, TLB_DISCARD_WRITE to slow flags
[PATCH v3 0/9] target/riscv/kvm: CSR related fixes
2025-04-25 16:43 UTC (11+ messages)
` [PATCH v3 1/9] target/riscv/kvm: minor fixes/tweaks
` [PATCH v3 2/9] target/riscv/kvm: fix leak in kvm_riscv_init_multiext_cfg()
` [PATCH v3 3/9] target/riscv/kvm: turn u32/u64 reg functions into macros
` [PATCH v3 4/9] target/riscv/kvm: turn kvm_riscv_reg_id_ulong() into a macro
` [PATCH v3 5/9] target/riscv/kvm: add kvm_csr_cfgs[]
` [PATCH v3 6/9] target/riscv/kvm: do not read unavailable CSRs
` [PATCH v3 7/9] target/riscv/kvm: add senvcfg CSR
` [PATCH v3 8/9] target/riscv: widen scounteren to target_ulong
` [PATCH v3 9/9] target/riscv/kvm: add scounteren CSR
[PATCH 0/4] Fix qemu-img bench issues and improve checks
2025-04-25 16:10 UTC (7+ messages)
` [PATCH 2/4] qemu-img: fix offset calculation in bench
` [PATCH 3/4] qemu-img: prevent stack overflow in bench by using bottom half
` [PATCH 4/4] qemu-img: improve queue depth validation in img_bench
[PATCH 0/3] [RESEND] block: unify block and fdmon io_uring
2025-04-25 15:51 UTC (3+ messages)
` [PATCH 1/3] aio-posix: treat io_uring setup failure as fatal
[PATCH v4 00/11] target/i386/kvm/pmu: PMU Enhancement, Bugfix and Cleanup
2025-04-25 15:45 UTC (4+ messages)
` [PATCH v4 01/11] [DO NOT MERGE] i386/cpu: Consolidate the helper to get Host's vendor
[PULL 00/58] Misc single binary patches for 2025-04-25
2025-04-25 15:28 UTC (34+ messages)
` [PULL 07/58] target/sparc: Register CPUClass:list_cpus
` [PULL 12/58] qom: Have class_base_init() take a const data argument
` [PULL 14/58] qom: Constify TypeInfo::class_data
` [PULL 18/58] hw/core: Get default_cpu_type calling machine_class_default_cpu_type()
` [PULL 19/58] hw/core/cpu: gdb_arch_name string should not be freed
` [PULL 20/58] gdbstub: Allow gdb_core_xml_file to be set at runtime
` [PULL 21/58] target/arm: Handle AArch64 in TYPE_ARM_CPU gdb_arch_name
` [PULL 22/58] target/arm: Handle gdb_core_xml_file in TYPE_ARM_CPU
` [PULL 26/58] target/mips: Fix MIPS16e translation
` [PULL 28/58] hw/usb/hcd-xhci: Unmap canceled packet
` [PULL 31/58] hw/net/can: Fix type conflict of GLib function pointers
` [PULL 32/58] contrib/plugins: "
` [PULL 36/58] pc-bios: Move device tree files in their own subdir
` [PULL 37/58] meson: Use has_header_symbol() to check getcpu()
` [PULL 39/58] meson: Share common C source prefixes
` [PULL 40/58] meson: Use osdep_prefix for strchrnul()
` [PULL 41/58] system/kvm: make functions accessible from common code
` [PULL 42/58] accel/tcg: Correct list of included headers in tcg-stub.c
` [PULL 44/58] linux-user/elfload: Use target_needs_bswap()
` [PULL 45/58] accel/kvm: "
` [PULL 46/58] target/mips: Check CPU endianness at runtime using env_is_bigendian()
` [PULL 47/58] target/xtensa: Evaluate TARGET_BIG_ENDIAN at compile time
` [PULL 48/58] hw/mips: "
` [PULL 49/58] hw/microblaze: "
` [PULL 50/58] qapi: Rename TargetInfo structure as QemuTargetInfo
` [PULL 51/58] qemu: Introduce target_cpu_type()
` [PULL 52/58] cpus: Replace CPU_RESOLVING_TYPE -> target_cpu_type()
` [PULL 53/58] cpus: Move target-agnostic methods out of cpu-target.c
` [PULL 54/58] accel: Implement accel_init_ops_interfaces() for both system/user mode
` [PULL 55/58] accel: Include missing 'qemu/accel.h' header in accel-internal.h
` [PULL 56/58] accel: Make AccelCPUClass structure target-agnostic
` [PULL 57/58] accel: Move target-agnostic code from accel-target.c -> accel-common.c
` [PULL 58/58] qemu: Convert target_name() to TargetInfo API
[PATCH] block： change type of bytes from int to int64_t for *bdrv_aio_pdiscard
2025-04-25 15:36 UTC (5+ messages)
[PATCH v2] hw/loongarch/virt: Get physical entry address with elf file
2025-04-25 15:33 UTC (2+ messages)
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