messages from 2025-10-02 16:47:51 to 2025-10-03 14:22:08 UTC [more...]
[PATCH v6 0/9] tests/functional: Adapt reverse_debugging to run w/o Avocado
2025-10-03 14:18 UTC (7+ messages)
` [PATCH v6 3/9] tests/functional: Provide GDB to the functional tests
` [PATCH v6 4/9] tests/functional: Add GDB class
` [PATCH v6 5/9] tests/functional: replace avocado process with subprocess
` [PATCH v6 6/9] tests/functional: drop datadrainer class in reverse debugging
` [PATCH v6 7/9] tests/functional: Add decorator to skip test on missing env vars
` [PATCH v6 8/9] tests/functional: Adapt reverse_debugging to run w/o Avocado
[PATCH v1 0/2] Implement -run-with exit-with-parent=on
2025-10-03 14:12 UTC (5+ messages)
` [PATCH v1 1/2] "
` [PATCH v1 2/2] tests/qtest: Use exit-with-parent=on in qtest invocations
[PATCH 00/14] Fix memory region use-after-finalization
2025-10-03 14:01 UTC (8+ messages)
` [PATCH 01/14] hw/pci-bridge: Do not assume immediate MemoryRegion finalization
` [PATCH 02/14] qdev: Automatically delete memory subregions
[PATCH V5 00/19] Live update: cpr-exec
2025-10-03 13:36 UTC (8+ messages)
[PATCH v5 0/9] tests/functional: Adapt reverse_debugging to run w/o Avocado
2025-10-03 13:30 UTC (4+ messages)
[PATCH v2 00/33] single-binary: Make riscv cpu.h target independent
2025-10-03 12:57 UTC (83+ messages)
` [PATCH v2 01/33] target/riscv: Use 32 bits for misa extensions
` [PATCH v2 02/33] target/riscv: Fix size of trivial CPUArchState fields
` [PATCH v2 03/33] target/riscv: Fix size of mhartid
` [PATCH v2 04/33] target/riscv: Bugfix riscv_pmu_ctr_get_fixed_counters_val()
` [PATCH v2 05/33] target/riscv: Combine mhpmevent and mhpmeventh
` [PATCH v2 06/33] target/riscv: Combine mcyclecfg and mcyclecfgh
` [PATCH v2 07/33] target/riscv: Combine minstretcfg and minstretcfgh
` [PATCH v2 08/33] target/riscv: Combine mhpmcounter and mhpmcounterh
` [PATCH v2 09/33] target/riscv: Fix size of gpr and gprh
` [PATCH v2 10/33] target/riscv: Fix size of vector CSRs
` [PATCH v2 11/33] target/riscv: Fix size of pc, load_[val|res]
` [PATCH v2 12/33] target/riscv: Fix size of frm and fflags
` [PATCH v2 13/33] target/riscv: Fix size of badaddr and bins
` [PATCH v2 14/33] target/riscv: Fix size of guest_phys_fault_addr
` [PATCH v2 15/33] target/riscv: Fix size of priv_ver and vext_ver
` [PATCH v2 16/33] target/riscv: Fix size of retxh
` [PATCH v2 17/33] target/riscv: Fix size of ssp
` [PATCH v2 18/33] target/riscv: Fix size of excp_uw2
` [PATCH v2 19/33] target/riscv: Fix size of sw_check_code
` [PATCH v2 20/33] target/riscv: Fix size of priv
` [PATCH v2 21/33] target/riscv: Fix size of gei fields
` [PATCH v2 22/33] target/riscv: Fix size of [m|s|vs]iselect fields
` [PATCH v2 23/33] target/riscv: Fix arguments to board IMSIC emulation callbacks
` [PATCH v2 24/33] target/riscv: Fix size of irq_overflow_left
` [PATCH v2 25/33] target/riscv: Indent PMUFixedCtrState correctly
` [PATCH v2 26/33] target/riscv: Replace target_ulong in riscv_cpu_get_trap_name()
` [PATCH v2 27/33] target/riscv: Replace target_ulong in riscv_ctr_add_entry()
` [PATCH v2 28/33] target/riscv: Fix size of trigger data
` [PATCH v2 29/33] target/riscv: Fix size of mseccfg
` [PATCH v2 30/33] target/riscv: Move debug.h include away from cpu.h
` [PATCH v2 31/33] target/riscv: Move CSR declarations to separate csr.h header
` [PATCH v2 32/33] target/riscv: Introduce externally facing CSR access functions
` [PATCH v2 33/33] target/riscv: Make pmp.h target_ulong agnostic
[PATCH v2] aspeed: Don't set 'auto_create_sdcard'
2025-10-03 12:48 UTC (2+ messages)
[PULL v2 00/13] Error reporting patches for 2025-09-30
2025-10-03 11:54 UTC (2+ messages)
[PULL 00/13] QTest patches for 2025-10-01
2025-10-03 11:55 UTC (2+ messages)
[PULL 00/16] Tracing patches
2025-10-03 11:54 UTC (2+ messages)
[PATCH v2 0/2] isapc: remove support for -cpu host and -cpu max
2025-10-03 11:46 UTC (3+ messages)
[PATCH v8 0/5] NVMe: Add SPDM over the storage transport support
2025-10-03 11:39 UTC (6+ messages)
` [PATCH v8 1/5] spdm-socket: add seperate send/recv functions
` [PATCH v8 2/5] spdm: add spdm storage transport virtual header
` [PATCH v8 3/5] hw/nvme: add NVMe Admin Security SPDM support
` [PATCH v8 4/5] spdm: define SPDM transport enum types
` [PATCH v8 5/5] hw/nvme: connect SPDM over NVMe Security Send/Recv
[PATCH v10 00/13] riscv: Add support for MIPS P8700 CPU
2025-10-03 10:45 UTC (14+ messages)
` [PATCH v10 01/13] hw/intc: Allow gaps in hartids for aclint and aplic
` [PATCH v10 04/13] target/riscv: Add MIPS P8700 CSRs
` [PATCH v10 03/13] target/riscv: Add MIPS P8700 CPU
` [PATCH v10 02/13] target/riscv: Add cpu_set_exception_base
` [PATCH v10 05/13] target/riscv: Add mips.ccmov instruction
` [PATCH v10 06/13] target/riscv: Add mips.pref instruction
` [PATCH v10 07/13] target/riscv: Add Xmipslsp instructions
` [PATCH v10 08/13] hw/misc: Add RISC-V CMGCR device implementation
` [PATCH v10 09/13] hw/misc: Add RISC-V CPC "
` [PATCH v10 11/13] hw/riscv: Add support for MIPS Boston-aia board mode
` [PATCH v10 12/13] riscv/boston-aia: Add an e1000e NIC in slot 0 func 1
` [PATCH v10 10/13] hw/riscv: Add support for RISCV CPS
` [PATCH v10 13/13] test/functional: Add test for boston-aia board
[PATCH v9 00/13] riscv: Add support for MIPS P8700 CPU
2025-10-03 10:40 UTC (7+ messages)
` [PATCH v9 02/13] target/riscv: Add cpu_set_exception_base
` [PATCH v9 13/13] test/functional: Add test for boston-aia board
[PULL 0/5] vfio queue
2025-10-03 10:33 UTC (6+ messages)
` [PULL 1/5] vfio: Remove workaround for kernel DMA unmap overflow bug
` [PULL 2/5] system/iommufd: Use uint64_t type for IOVA mapping size
` [PULL 3/5] hw/vfio: Reorder vfio_container_query_dirty_bitmap() trace format
` [PULL 4/5] hw/vfio: Avoid ram_addr_t in vfio_container_query_dirty_bitmap()
` [PULL 5/5] hw/vfio: Use uint64_t for IOVA mapping size in vfio_container_dma_*map
[PATCH v1 0/5] Update to test ASPEED SDK v09.08
2025-10-03 10:19 UTC (7+ messages)
` [PATCH v1 1/5] tests/functional/arm/test_aspeed_ast1030: Update test ASPEED SDK v03.03
` [PATCH v1 2/5] tests/functional/arm/test_aspeed_ast2500: Update test ASPEED SDK v09.08
` [PATCH v1 3/5] tests/functional/arm/test_aspeed_ast2600: "
` [PATCH v1 4/5] tests/functional/aarch64/test_aspeed_ast2700: Update test ASPEED SDK v09.08 for A1
` [PATCH v1 5/5] tests/functional/aarch64/test_aspeed_ast2700: Move eth2 IP check into common function
` [SPAM] [PATCH v1 0/5] Update to test ASPEED SDK v09.08
[Bug 2123828] Re: RISC-V: incorrect emulation of load and store on big-endian systems
2025-10-03 10:10 UTC (4+ messages)
[PATCH 0/3] migration: Add support for mapped-ram with snapshots
2025-10-03 9:47 UTC (4+ messages)
` [PATCH 1/3] migration: add FEATURE_SEEKABLE to QIOChannelBlock
[RFC PATCH 0/2] target/arm: Allow aarch64=off for TCG
2025-10-03 9:28 UTC (2+ messages)
[PATCH] aspeed: Set 'auto_create_sdcard' to false
2025-10-03 8:30 UTC (2+ messages)
[RFC 0/3] Mitigation of migration failures accross different host kernels
2025-10-03 8:10 UTC (5+ messages)
` [RFC 1/3] target/arm/cpu: Add new CPU property for KVM regs to hide
[PATCH 0/3] block: use pwrite_zeroes_alignment when writing first sector
2025-10-03 8:04 UTC (8+ messages)
` [PATCH 1/3] file-posix: populate pwrite_zeroes_alignment
` [PATCH 2/3] block: use pwrite_zeroes_alignment when writing first sector
` [PATCH 3/3] iotests: add Linux loop device image creation test
[PATCH v4 0/3] Support VBOOTROM to ast2700fc machine
2025-10-03 7:26 UTC (6+ messages)
` [PATCH v4 3/3] tests/functional/aarch64/test_aspeed_ast2700fc: Add vbootrom test
[PULL 00/26] riscv-to-apply queue
2025-10-03 3:27 UTC (27+ messages)
` [PULL 01/26] hw/riscv/riscv-iommu: Fix MSI table size limit
` [PULL 02/26] docs/interop/firmware: Add riscv64 to FirmwareArchitecture
` [PULL 03/26] linux-user/syscall.c: sync RISC-V hwprobe with Linux
` [PULL 04/26] target/riscv: implement MonitorDef HMP API
` [PULL 05/26] roms/opensbi: Update to v1.7
` [PULL 06/26] hw/char: sifive_uart: Raise IRQ according to the Tx/Rx watermark thresholds
` [PULL 07/26] hw/char: sifive_uart: Avoid pushing Tx FIFO when size is zero
` [PULL 08/26] hw/char: sifive_uart: Remove outdated comment about Tx FIFO
` [PULL 09/26] hw/char: sifive_uart: Add newline to error message
` [PULL 10/26] hw/intc: Save time_delta in RISC-V mtimer VMState
` [PULL 11/26] migration: Add support for a variable-length array of UINT32 pointers
` [PULL 12/26] hw/intc: Save timers array in RISC-V mtimer VMState
` [PULL 13/26] target/riscv: Save stimer and vstimer in CPU vmstate
` [PULL 14/26] target/riscv/kvm: Use riscv_cpu_is_32bit() when handling SBI_DBCN reg
` [PULL 15/26] target/riscv: use riscv_csrr in riscv_csr_read
` [PULL 16/26] qemu/osdep: align memory allocations to 2M on RISC-V
` [PULL 17/26] target/riscv: do not use translator_ldl in opcode_at
` [PULL 18/26] target/riscv: Fix the mepc when sspopchk triggers the exception
` [PULL 19/26] target/riscv: Fix SSP CSR error handling in VU/VS mode
` [PULL 20/26] target/riscv: Fix ssamoswap error handling
` [PULL 21/26] target/riscv: rvv: Replace checking V by checking Zve32x
` [PULL 22/26] target/riscv: rvv: Modify minimum VLEN according to enabled vector extensions
` [PULL 23/26] target/riscv: rvv: Fix vslide1[up|down].vx unexpected result when XLEN=32 and SEW=64
` [PULL 24/26] hw/riscv/riscv-iommu: Fixup PDT Nested Walk
` [PULL 25/26] target/riscv: Fix endianness swap on compressed instructions
` [PULL 26/26] docs: riscv-iommu: Update status of kernel support
[PATCH v7 0/5] NVMe: Add SPDM over the storage transport support
2025-10-03 2:04 UTC (9+ messages)
` [PATCH v7 1/5] spdm-socket: add seperate send/recv functions
` [PATCH v7 3/5] hw/nvme: add NVMe Admin Security SPDM support
` [PATCH v7 4/5] spdm: define SPDM transport enum types
` [PATCH v7 5/5] hw/nvme: connect SPDM over NVMe Security Send/Recv
[PULL 00/30] riscv-to-apply queue
2025-10-03 1:39 UTC (4+ messages)
` [PULL 21/30] target/riscv: Implement privilege mode filtering for cycle/instret
[PATCH v2] docs: riscv-iommu: Update status of kernel support
2025-10-03 1:28 UTC (2+ messages)
[PATCH v3 RESEND] hw/riscv/virt: Add acpi ged and powerdown support
2025-10-03 1:25 UTC (3+ messages)
[PATCH] target/riscv: Fix endianness swap on compressed instructions
2025-10-03 1:06 UTC (2+ messages)
[PATCH 0/2] FEAT_GCS firmware update for test_rme_*
2025-10-02 22:01 UTC (6+ messages)
` [PATCH 1/2] Update tf-rmm to support FEAT_S1PIE
` [PATCH 2/2] Enable firmware support for PIE and GCS
[PATCH v4 00/27] hw/arm/virt: Add support for user-creatable accelerated SMMUv3
2025-10-02 18:35 UTC (6+ messages)
` [PATCH v4 08/27] hw/arm/smmuv3-accel: Add set/unset_iommu_device callback
[PATCH] docs/system/keys: fix incorrect reset scaling key binding
2025-10-02 18:03 UTC (5+ messages)
[PATCH v2 00/18] system/physmem: Extract API out of 'system/ram_addr.h' header
2025-10-02 17:38 UTC (5+ messages)
` [PATCH v2 06/18] hw: Remove unnecessary "
[PATCH v5 00/27] Implementing a MSHV (Microsoft Hypervisor) accelerator
2025-10-02 17:15 UTC (28+ messages)
` [PATCH 01/27] accel: Add Meson and config support for MSHV accelerator
` [PATCH 02/27] target/i386/emulate: Allow instruction decoding from stream
` [PATCH 03/27] target/i386/mshv: Add x86 decoder/emu implementation
` [PATCH 04/27] hw/intc: Generalize APIC helper names from kvm_* to accel_*
` [PATCH 05/27] include/hw/hyperv: Add MSHV ABI header definitions
` [PATCH 06/27] linux-headers/linux: Add mshv.h headers
` [PATCH 07/27] accel/mshv: Add accelerator skeleton
` [PATCH 08/27] accel/mshv: Register memory region listeners
` [PATCH 09/27] accel/mshv: Initialize VM partition
` [PATCH 10/27] accel/mshv: Add vCPU creation and execution loop
` [PATCH 11/27] accel/mshv: Add vCPU signal handling
` [PATCH 12/27] target/i386/mshv: Add CPU create and remove logic
` [PATCH 13/27] target/i386/mshv: Implement mshv_store_regs()
` [PATCH 14/27] target/i386/mshv: Implement mshv_get_standard_regs()
` [PATCH 15/27] target/i386/mshv: Implement mshv_get_special_regs()
` [PATCH 16/27] target/i386/mshv: Implement mshv_arch_put_registers()
` [PATCH 17/27] target/i386/mshv: Set local interrupt controller state
` [PATCH 18/27] target/i386/mshv: Register CPUID entries with MSHV
` [PATCH 19/27] target/i386/mshv: Register MSRs "
` [PATCH 20/27] target/i386/mshv: Integrate x86 instruction decoder/emulator
` [PATCH 21/27] target/i386/mshv: Write MSRs to the hypervisor
` [PATCH 22/27] target/i386/mshv: Implement mshv_vcpu_run()
` [PATCH 23/27] accel/mshv: Handle overlapping mem mappings
` [PATCH 24/27] qapi/accel: Allow to query mshv capabilities
` [PATCH 25/27] target/i386/mshv: Use preallocated page for hvcall
` [PATCH 26/27] docs: Add mshv to documentation
` [PATCH 27/27] MAINTAINERS: Add maintainers for mshv accelerator
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