From: WANG Xuerui <i@xen0n.name>
To: Richard Henderson <richard.henderson@linaro.org>,
Qi Hu <huqi@loongson.cn>, WANG Xuerui <git@xen0n.name>
Cc: qemu-devel@nongnu.org
Subject: Re: [PATCH v4] tcg/loongarch64: Add direct jump support
Date: Fri, 21 Oct 2022 08:04:17 +0800 [thread overview]
Message-ID: <A99B67E2-6F23-40CA-807C-A66366D0C533@xen0n.name> (raw)
In-Reply-To: <9a9fea07-2242-5aff-ea94-cfc119207f09@linaro.org>
On October 21, 2022 6:42:58 AM GMT+08:00, Richard Henderson <richard.henderson@linaro.org> wrote:
>Fixed a minor nit:
>
>> +void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
>> + uintptr_t jmp_rw, uintptr_t addr)
>> +{
>> + tcg_insn_unit i1, i2;
>> + ptrdiff_t upper, lower;
>> + ptrdiff_t offset = (ptrdiff_t)(addr - jmp_rx) >> 2;
>> +
>> + if (offset == sextreg(offset, 0, 26)) {
>> + i1 = encode_sd10k16_insn(OPC_B, offset);
>> + i2 = NOP;
>> + } else {
>> + tcg_debug_assert(offset == sextreg(offset, 0, 36));
>
>This assert is smaller...
>
>> +/*
>> + * PCADDU18I + JIRL sequence can give 20 + 16 + 2 = 38 bits
>> + * signed offset, which is +/- 128 GiB.
>> + */
>> +#define MAX_CODE_GEN_BUFFER_SIZE (128 * GiB)
>
>... than the correct calculation here.
Actually no... the offset above is pre-shifted so 36 is exactly 20 (pcaddu18i) + 16 (jirl). The LoongArch assembly gotchas hit hard...
prev parent reply other threads:[~2022-10-21 0:18 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-15 9:27 [PATCH v4] tcg/loongarch64: Add direct jump support Qi Hu
2022-10-15 15:06 ` WANG Xuerui
2022-10-16 10:04 ` Richard Henderson
2022-10-20 22:42 ` Richard Henderson
2022-10-21 0:04 ` WANG Xuerui [this message]
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