From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=44397 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PaCBK-0003bR-NV for qemu-devel@nongnu.org; Tue, 04 Jan 2011 14:04:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PaCBC-0004ia-EI for qemu-devel@nongnu.org; Tue, 04 Jan 2011 14:04:24 -0500 Received: from mail-pv0-f173.google.com ([74.125.83.173]:34939) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PaCBC-0004iM-6F for qemu-devel@nongnu.org; Tue, 04 Jan 2011 14:04:22 -0500 Received: by pvh11 with SMTP id 11so3639418pvh.4 for ; Tue, 04 Jan 2011 11:04:21 -0800 (PST) MIME-Version: 1.0 In-Reply-To: <3e70a4781ce732231de2b6f168cdc2803b1fb7cc.1294055704.git.chouteau@adacore.com> References: <27ea9bf7c9bfef1928cdca9ec6b9a48171244385.1294055704.git.chouteau@adacore.com> <8e4a3a60873787fca105de9791018794970a6c4d.1294055704.git.chouteau@adacore.com> <3e70a4781ce732231de2b6f168cdc2803b1fb7cc.1294055704.git.chouteau@adacore.com> From: Blue Swirl Date: Tue, 4 Jan 2011 19:04:00 +0000 Message-ID: Subject: Re: [Qemu-devel] [PATCH v2 4/6] Header file for the GRLIB components. Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Fabien Chouteau Cc: qemu-devel@nongnu.org On Mon, Jan 3, 2011 at 2:07 PM, Fabien Chouteau wrot= e: > > Signed-off-by: Fabien Chouteau > --- > =C2=A0hw/grlib.h | =C2=A0121 ++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++ > =C2=A01 files changed, 121 insertions(+), 0 deletions(-) > > diff --git a/hw/grlib.h b/hw/grlib.h > new file mode 100644 > index 0000000..bb3c01e > --- /dev/null > +++ b/hw/grlib.h > @@ -0,0 +1,121 @@ > +/* > + * QEMU GRLIB Components > + * > + * Copyright (c) 2010-2011 AdaCore > + * > + * Permission is hereby granted, free of charge, to any person obtaining= a copy > + * of this software and associated documentation files (the "Software"),= to deal > + * in the Software without restriction, including without limitation the= rights > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or = sell > + * copies of the Software, and to permit persons to whom the Software is > + * furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice shall be includ= ed in > + * all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRE= SS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILI= TY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHA= LL > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR = OTHER > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISI= NG FROM, > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALING= S IN > + * THE SOFTWARE. > + */ > + > +#ifndef _GRLIB_H_ > +#define _GRLIB_H_ > + > +#include "qdev.h" > +#include "sysbus.h" > + > +/* Emulation of GrLib device is base on the GRLIB IP Core User's Manual: > + * http://www.gaisler.com/products/grlib/grip.pdf > + */ > + > +/* IRQMP */ > + > +void grlib_irqmp_set_irq(void *opaque, int irq, int level); > + > +void grlib_irqmp_ack(DeviceState *dev, int intno); > + > +static inline > +DeviceState *grlib_irqmp_create(target_phys_addr_t =C2=A0 base, > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0CPUState =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0*env, > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0qemu_irq =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 **cpu_irqs, > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint32_t =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 nr_irqs) > +{ > + =C2=A0 =C2=A0DeviceState *dev; > + > + =C2=A0 =C2=A0assert(cpu_irqs !=3D NULL); > + > + =C2=A0 =C2=A0dev =3D qdev_create(NULL, "grlib,irqmp"); > + =C2=A0 =C2=A0qdev_prop_set_ptr(dev, "cpustate", env); > + > + =C2=A0 =C2=A0if (qdev_init(dev)) { > + =C2=A0 =C2=A0 =C2=A0 =C2=A0return NULL; > + =C2=A0 =C2=A0} > + > + =C2=A0 =C2=A0env->irq_manager =3D dev; > + > + =C2=A0 =C2=A0sysbus_mmio_map(sysbus_from_qdev(dev), 0, base); > + > + =C2=A0 =C2=A0*cpu_irqs =3D qemu_allocate_irqs(grlib_irqmp_set_irq, > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 dev, > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 nr_irqs); > + > + =C2=A0 =C2=A0return dev; > +} > + > +/* GPTimer */ > + > +static inline > +DeviceState *grlib_gptimer_create(target_phys_addr_t =C2=A0base, > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint32_t =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0nr_timers, > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint32_t =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0freq, > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0qemu_irq =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 *cpu_irqs, > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0int =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 base_irq) > +{ > + =C2=A0 =C2=A0DeviceState *dev; > + =C2=A0 =C2=A0int i; > + > + =C2=A0 =C2=A0dev =3D qdev_create(NULL, "grlib,gptimer"); > + =C2=A0 =C2=A0qdev_prop_set_uint32(dev, "nr-timers", nr_timers); > + =C2=A0 =C2=A0qdev_prop_set_uint32(dev, "frequency", freq); > + =C2=A0 =C2=A0qdev_prop_set_uint32(dev, "irq-line", base_irq); > + > + =C2=A0 =C2=A0if (qdev_init(dev)) { > + =C2=A0 =C2=A0 =C2=A0 =C2=A0return NULL; > + =C2=A0 =C2=A0} > + > + =C2=A0 =C2=A0sysbus_mmio_map(sysbus_from_qdev(dev), 0, base); > + > + =C2=A0 =C2=A0for (i =3D 0; i < nr_timers; i++) Missing braces.