From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=38482 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PnzuV-0002Bk-04 for qemu-devel@nongnu.org; Fri, 11 Feb 2011 15:48:12 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PnzuR-0001DX-NY for qemu-devel@nongnu.org; Fri, 11 Feb 2011 15:48:10 -0500 Received: from mail-vx0-f173.google.com ([209.85.220.173]:51974) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PnzuR-0001DI-Hh for qemu-devel@nongnu.org; Fri, 11 Feb 2011 15:48:07 -0500 Received: by vxb40 with SMTP id 40so1593750vxb.4 for ; Fri, 11 Feb 2011 12:48:07 -0800 (PST) MIME-Version: 1.0 In-Reply-To: <1297379530-23487-14-git-send-email-michael@walle.cc> References: <1297379530-23487-1-git-send-email-michael@walle.cc> <1297379530-23487-14-git-send-email-michael@walle.cc> From: Blue Swirl Date: Fri, 11 Feb 2011 22:47:45 +0200 Message-ID: Subject: Re: [Qemu-devel] [PATCH 13/17] lm32: EVR32 and uclinux BSP Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Michael Walle Cc: "Edgar E. Iglesias" , Richard Henderson , qemu-devel@nongnu.org, Alexander Graf On Fri, Feb 11, 2011 at 1:12 AM, Michael Walle wrote: > This patch adds support for the following two BSPs: > =C2=A0- LM32 EVR32 BSP (as used by RTEMS) > =C2=A0- uclinux BSP by Theobroma Systems > > Signed-off-by: Michael Walle > --- > =C2=A0Makefile.target =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0| =C2=A0 =C2=A03 + > =C2=A0default-configs/lm32-softmmu.mak | =C2=A0 =C2=A04 + > =C2=A0hw/lm32_boards.c =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 | =C2=A0295 ++++++++++++++++++++++++++++++++++++++ > =C2=A03 files changed, 302 insertions(+), 0 deletions(-) > =C2=A0create mode 100644 default-configs/lm32-softmmu.mak > =C2=A0create mode 100644 hw/lm32_boards.c > > diff --git a/Makefile.target b/Makefile.target > index 185cc96..77d1ea3 100644 > --- a/Makefile.target > +++ b/Makefile.target > @@ -247,6 +247,9 @@ obj-ppc-y +=3D xilinx_timer.o > =C2=A0obj-ppc-y +=3D xilinx_uartlite.o > =C2=A0obj-ppc-y +=3D xilinx_ethlite.o > > +# LM32 boards > +obj-lm32-y +=3D lm32_boards.o > + > =C2=A0# LM32 peripherals > =C2=A0obj-lm32-y +=3D lm32_pic.o > =C2=A0obj-lm32-y +=3D lm32_pic_cpu.o > diff --git a/default-configs/lm32-softmmu.mak b/default-configs/lm32-soft= mmu.mak > new file mode 100644 > index 0000000..ab774a2 > --- /dev/null > +++ b/default-configs/lm32-softmmu.mak > @@ -0,0 +1,4 @@ > +# Default configuration for lm32-softmmu > + > +CONFIG_PTIMER=3Dy > +CONFIG_PFLASH_CFI02=3Dy > diff --git a/hw/lm32_boards.c b/hw/lm32_boards.c > new file mode 100644 > index 0000000..c174c17 > --- /dev/null > +++ b/hw/lm32_boards.c > @@ -0,0 +1,295 @@ > +/* > + * =C2=A0QEMU models for LatticeMico32 uclinux and evr32 boards. > + * > + * =C2=A0Copyright (c) 2010 Michael Walle > + * > + * This library is free software; you can redistribute it and/or > + * modify it under the terms of the GNU Lesser General Public > + * License as published by the Free Software Foundation; either > + * version 2 of the License, or (at your option) any later version. > + * > + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. =C2=A0See the GN= U > + * Lesser General Public License for more details. > + * > + * You should have received a copy of the GNU Lesser General Public > + * License along with this library; if not, see . > + */ > + > +#include "sysbus.h" > +#include "hw.h" > +#include "net.h" > +#include "flash.h" > +#include "sysemu.h" > +#include "devices.h" > +#include "boards.h" > +#include "loader.h" > +#include "blockdev.h" > +#include "elf.h" > +#include "lm32_hwsetup.h" > +#include "lm32.h" > + > +struct reset_info { CODING_STYLE: ResetInfo, missing typedef. > + =C2=A0 =C2=A0CPUState *env; > + =C2=A0 =C2=A0uint32_t bootstrap_pc; > + =C2=A0 =C2=A0uint32_t flash_base; > + =C2=A0 =C2=A0uint32_t hwsetup_base; > + =C2=A0 =C2=A0uint32_t initrd_base; > + =C2=A0 =C2=A0uint32_t initrd_size; > + =C2=A0 =C2=A0uint32_t cmdline_base; > +}; > + > +qemu_irq *lm32_pic_init_cpu(CPUState *env); This belongs to a header file. > + > +static void main_cpu_reset(void *opaque) > +{ > + =C2=A0 =C2=A0struct reset_info *reset_info =3D opaque; > + =C2=A0 =C2=A0CPUState *env =3D reset_info->env; > + > + =C2=A0 =C2=A0cpu_reset(env); > + > + =C2=A0 =C2=A0/* init defaults */ > + =C2=A0 =C2=A0env->pc =3D reset_info->bootstrap_pc; > + =C2=A0 =C2=A0env->regs[R_R1] =3D reset_info->hwsetup_base; > + =C2=A0 =C2=A0env->regs[R_R2] =3D reset_info->cmdline_base; > + =C2=A0 =C2=A0env->regs[R_R3] =3D reset_info->initrd_base; > + =C2=A0 =C2=A0env->regs[R_R4] =3D reset_info->initrd_base + reset_info->= initrd_size; > + =C2=A0 =C2=A0env->eba =3D reset_info->flash_base; > + =C2=A0 =C2=A0env->deba =3D reset_info->flash_base; > +} > + > +static void lm32_evr_init(ram_addr_t ram_size_not_used, > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0const char *boot_device, > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0const char *kernel_filename, > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0const char *kernel_cmdline, > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0const char *initrd_filename, const char *cpu_model) > +{ > + =C2=A0 =C2=A0CPUState *env; > + =C2=A0 =C2=A0DriveInfo *dinfo; > + =C2=A0 =C2=A0ram_addr_t phys_ram; > + =C2=A0 =C2=A0ram_addr_t phys_flash; > + =C2=A0 =C2=A0qemu_irq *cpu_irq, irq[32]; > + =C2=A0 =C2=A0DeviceState *dev; > + =C2=A0 =C2=A0struct reset_info *reset_info; > + =C2=A0 =C2=A0int i; > + > + =C2=A0 =C2=A0/* memory map */ > + =C2=A0 =C2=A0ram_addr_t flash_base =C2=A0 =C2=A0=3D 0x04000000; > + =C2=A0 =C2=A0size_t flash_sector_size =3D 256 * 1024; > + =C2=A0 =C2=A0size_t flash_size =C2=A0 =C2=A0 =C2=A0 =C2=A0=3D 32 * 1024= * 1024; > + =C2=A0 =C2=A0ram_addr_t ram_base =C2=A0 =C2=A0 =C2=A0=3D 0x08000000; > + =C2=A0 =C2=A0size_t ram_size =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0=3D 64 *= 1024 * 1024; > + =C2=A0 =C2=A0ram_addr_t timer0_base =C2=A0 =3D 0x80002000; > + =C2=A0 =C2=A0ram_addr_t uart0_base =C2=A0 =C2=A0=3D 0x80006000; > + =C2=A0 =C2=A0ram_addr_t timer1_base =C2=A0 =3D 0x8000a000; > + =C2=A0 =C2=A0int uart0_irq =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0=3D= 0; > + =C2=A0 =C2=A0int timer0_irq =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D 1; > + =C2=A0 =C2=A0int timer1_irq =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D 3; > + > + =C2=A0 =C2=A0reset_info =3D qemu_mallocz(sizeof(struct reset_info)); > + > + =C2=A0 =C2=A0if (cpu_model =3D=3D NULL) { > + =C2=A0 =C2=A0 =C2=A0 =C2=A0cpu_model =3D "lm32-full"; > + =C2=A0 =C2=A0} > + =C2=A0 =C2=A0env =3D cpu_init(cpu_model); > + =C2=A0 =C2=A0reset_info->env =3D env; > + > + =C2=A0 =C2=A0reset_info->flash_base =3D flash_base; > + > + =C2=A0 =C2=A0phys_ram =3D qemu_ram_alloc(NULL, "lm32_evr.sdram", ram_si= ze); > + =C2=A0 =C2=A0cpu_register_physical_memory(ram_base, ram_size, phys_ram = | IO_MEM_RAM); > + > + =C2=A0 =C2=A0phys_flash =3D qemu_ram_alloc(NULL, "lm32_evr.flash", flas= h_size); > + =C2=A0 =C2=A0dinfo =3D drive_get(IF_PFLASH, 0, 0); > + =C2=A0 =C2=A0/* Spansion S29NS128P */ > + =C2=A0 =C2=A0pflash_cfi02_register(flash_base, phys_flash, > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0dinfo ? dinfo->bdrv : NULL, flash_sector_size, > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0flash_size / flash_sector_size, 1, 2, > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A00x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1); > + > + =C2=A0 =C2=A0cpu_irq =3D lm32_pic_init_cpu(env); > + =C2=A0 =C2=A0dev =3D lm32_pic_init(env, *cpu_irq); > + =C2=A0 =C2=A0for (i =3D 0; i < 32; i++) { > + =C2=A0 =C2=A0 =C2=A0 =C2=A0irq[i] =3D qdev_get_gpio_in(dev, i); > + =C2=A0 =C2=A0} > + > + =C2=A0 =C2=A0sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_ir= q]); > + =C2=A0 =C2=A0sysbus_create_simple("lm32-timer", timer0_base, irq[timer0= _irq]); > + =C2=A0 =C2=A0sysbus_create_simple("lm32-timer", timer1_base, irq[timer1= _irq]); > + > + =C2=A0 =C2=A0/* make sure juart isn't the first chardev */ > + =C2=A0 =C2=A0lm32_juart_init(env); > + > + =C2=A0 =C2=A0reset_info->bootstrap_pc =3D flash_base; > + > + =C2=A0 =C2=A0if (kernel_filename) { > + =C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t entry; > + =C2=A0 =C2=A0 =C2=A0 =C2=A0int kernel_size; > + > + =C2=A0 =C2=A0 =C2=A0 =C2=A0kernel_size =3D load_elf(kernel_filename, NU= LL, NULL, &entry, NULL, NULL, > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 1, ELF_MACHINE, 0); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0reset_info->bootstrap_pc =3D entry; > + > + =C2=A0 =C2=A0 =C2=A0 =C2=A0if (kernel_size < 0) { > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0kernel_size =3D load_image_tar= gphys(kernel_filename, ram_base, > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0ram_size); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0reset_info->bootstrap_pc =3D r= am_base; > + =C2=A0 =C2=A0 =C2=A0 =C2=A0} > + > + =C2=A0 =C2=A0 =C2=A0 =C2=A0if (kernel_size < 0) { > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0fprintf(stderr, "qemu: could n= ot load kernel '%s'\n", > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0ke= rnel_filename); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0exit(1); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0} > + =C2=A0 =C2=A0} > + > + =C2=A0 =C2=A0qemu_register_reset(main_cpu_reset, reset_info); > +} > + > +static void lm32_uclinux_init(ram_addr_t ram_size_not_used, > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0const char *boot_device, > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0const char *kernel_filename, > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0const char *kernel_cmdline, > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0const char *initrd_filename, const char *cpu_model) > +{ > + =C2=A0 =C2=A0CPUState *env; > + =C2=A0 =C2=A0DriveInfo *dinfo; > + =C2=A0 =C2=A0ram_addr_t phys_ram; > + =C2=A0 =C2=A0ram_addr_t phys_flash; > + =C2=A0 =C2=A0qemu_irq *cpu_irq, irq[32]; > + =C2=A0 =C2=A0DeviceState *dev; > + =C2=A0 =C2=A0struct hwsetup *hw; > + =C2=A0 =C2=A0struct reset_info *reset_info; > + =C2=A0 =C2=A0int i; > + > + =C2=A0 =C2=A0/* memory map */ > + =C2=A0 =C2=A0ram_addr_t flash_base =C2=A0 =C2=A0=3D 0x04000000; > + =C2=A0 =C2=A0size_t flash_sector_size =3D 256 * 1024; > + =C2=A0 =C2=A0size_t flash_size =C2=A0 =C2=A0 =C2=A0 =C2=A0=3D 32 * 1024= * 1024; > + =C2=A0 =C2=A0ram_addr_t ram_base =C2=A0 =C2=A0 =C2=A0=3D 0x08000000; > + =C2=A0 =C2=A0size_t ram_size =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0=3D 64 *= 1024 * 1024; > + =C2=A0 =C2=A0ram_addr_t uart0_base =C2=A0 =C2=A0=3D 0x80000000; > + =C2=A0 =C2=A0ram_addr_t timer0_base =C2=A0 =3D 0x80002000; > + =C2=A0 =C2=A0ram_addr_t timer1_base =C2=A0 =3D 0x80010000; > + =C2=A0 =C2=A0ram_addr_t timer2_base =C2=A0 =3D 0x80012000; > + =C2=A0 =C2=A0int uart0_irq =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0=3D= 0; > + =C2=A0 =C2=A0int timer0_irq =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D 1; > + =C2=A0 =C2=A0int timer1_irq =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D 20; > + =C2=A0 =C2=A0int timer2_irq =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D 21; > + =C2=A0 =C2=A0ram_addr_t hwsetup_base =C2=A0=3D 0x0bffe000; > + =C2=A0 =C2=A0ram_addr_t cmdline_base =C2=A0=3D 0x0bfff000; > + =C2=A0 =C2=A0ram_addr_t initrd_base =C2=A0 =3D 0x08400000; All above ram_addr_t should instead be target_phys_addr_t. > + =C2=A0 =C2=A0size_t initrd_max =C2=A0 =C2=A0 =C2=A0 =C2=A0=3D 0x0100000= 0; > + > + =C2=A0 =C2=A0reset_info =3D qemu_mallocz(sizeof(struct reset_info)); > + > + =C2=A0 =C2=A0if (cpu_model =3D=3D NULL) { > + =C2=A0 =C2=A0 =C2=A0 =C2=A0cpu_model =3D "lm32-full"; > + =C2=A0 =C2=A0} > + =C2=A0 =C2=A0env =3D cpu_init(cpu_model); > + =C2=A0 =C2=A0reset_info->env =3D env; > + > + =C2=A0 =C2=A0reset_info->flash_base =3D flash_base; > + > + =C2=A0 =C2=A0phys_ram =3D qemu_ram_alloc(NULL, "lm32_uclinux.sdram", ra= m_size); > + =C2=A0 =C2=A0cpu_register_physical_memory(ram_base, ram_size, phys_ram = | IO_MEM_RAM); > + > + =C2=A0 =C2=A0phys_flash =3D qemu_ram_alloc(NULL, "lm32_uclinux.flash", = flash_size); > + =C2=A0 =C2=A0dinfo =3D drive_get(IF_PFLASH, 0, 0); > + =C2=A0 =C2=A0/* Spansion S29NS128P */ > + =C2=A0 =C2=A0pflash_cfi02_register(flash_base, phys_flash, > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0dinfo ? dinfo->bdrv : NULL, flash_sector_size, > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0flash_size / flash_sector_size, 1, 2, > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A00x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1); > + > + =C2=A0 =C2=A0cpu_irq =3D lm32_pic_init_cpu(env); > + =C2=A0 =C2=A0dev =3D lm32_pic_init(env, *cpu_irq); > + =C2=A0 =C2=A0for (i =3D 0; i < 32; i++) { > + =C2=A0 =C2=A0 =C2=A0 =C2=A0irq[i] =3D qdev_get_gpio_in(dev, i); > + =C2=A0 =C2=A0} > + > + =C2=A0 =C2=A0sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_ir= q]); > + =C2=A0 =C2=A0sysbus_create_simple("lm32-timer", timer0_base, irq[timer0= _irq]); > + =C2=A0 =C2=A0sysbus_create_simple("lm32-timer", timer1_base, irq[timer1= _irq]); > + =C2=A0 =C2=A0sysbus_create_simple("lm32-timer", timer2_base, irq[timer2= _irq]); > + > + =C2=A0 =C2=A0/* make sure juart isn't the first chardev */ > + =C2=A0 =C2=A0lm32_juart_init(env); > + > + =C2=A0 =C2=A0reset_info->bootstrap_pc =3D flash_base; > + > + =C2=A0 =C2=A0if (kernel_filename) { > + =C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t entry; > + =C2=A0 =C2=A0 =C2=A0 =C2=A0int kernel_size; > + > + =C2=A0 =C2=A0 =C2=A0 =C2=A0kernel_size =3D load_elf(kernel_filename, NU= LL, NULL, &entry, NULL, NULL, > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 1, ELF_MACHINE, 0); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0reset_info->bootstrap_pc =3D entry; > + > + =C2=A0 =C2=A0 =C2=A0 =C2=A0if (kernel_size < 0) { > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0kernel_size =3D load_image_tar= gphys(kernel_filename, ram_base, > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0ram_size); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0reset_info->bootstrap_pc =3D r= am_base; > + =C2=A0 =C2=A0 =C2=A0 =C2=A0} > + > + =C2=A0 =C2=A0 =C2=A0 =C2=A0if (kernel_size < 0) { > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0fprintf(stderr, "qemu: could n= ot load kernel '%s'\n", > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0ke= rnel_filename); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0exit(1); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0} > + =C2=A0 =C2=A0} > + > + =C2=A0 =C2=A0/* generate a rom with the hardware description */ > + =C2=A0 =C2=A0hw =3D hwsetup_init(); > + =C2=A0 =C2=A0hwsetup_add_cpu(hw, "LM32", 75000000); > + =C2=A0 =C2=A0hwsetup_add_flash(hw, "flash", flash_base, flash_size); > + =C2=A0 =C2=A0hwsetup_add_ddr_sdram(hw, "ddr_sdram", ram_base, ram_size)= ; > + =C2=A0 =C2=A0hwsetup_add_timer(hw, "timer0", timer0_base, timer0_irq); > + =C2=A0 =C2=A0hwsetup_add_timer(hw, "timer1_dev_only", timer1_base, time= r1_irq); > + =C2=A0 =C2=A0hwsetup_add_timer(hw, "timer2_dev_only", timer2_base, time= r2_irq); > + =C2=A0 =C2=A0hwsetup_add_uart(hw, "uart", uart0_base, uart0_irq); > + =C2=A0 =C2=A0hwsetup_add_trailer(hw); > + =C2=A0 =C2=A0hwsetup_create_rom(hw, hwsetup_base); > + =C2=A0 =C2=A0hwsetup_free(hw); > + > + =C2=A0 =C2=A0reset_info->hwsetup_base =3D (uint32_t)hwsetup_base; This cast should be avoided by changing the type of field hwsetup_base. > + > + =C2=A0 =C2=A0if (kernel_cmdline && strlen(kernel_cmdline)) { > + =C2=A0 =C2=A0 =C2=A0 =C2=A0pstrcpy_targphys("cmdline", cmdline_base, TA= RGET_PAGE_SIZE, > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0kernel_cmdline); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0reset_info->cmdline_base =3D (uint32_t)cmdli= ne_base; > + =C2=A0 =C2=A0} > + > + =C2=A0 =C2=A0if (initrd_filename) { > + =C2=A0 =C2=A0 =C2=A0 =C2=A0size_t initrd_size; > + =C2=A0 =C2=A0 =C2=A0 =C2=A0initrd_size =3D load_image_targphys(initrd_f= ilename, initrd_base, > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0initrd_max); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0reset_info->initrd_base =3D (uint32_t)initrd= _base; > + =C2=A0 =C2=A0 =C2=A0 =C2=A0reset_info->initrd_size =3D (uint32_t)initrd= _size; Ditto > + =C2=A0 =C2=A0} > + > + =C2=A0 =C2=A0qemu_register_reset(main_cpu_reset, reset_info); > +} > + > +static QEMUMachine lm32_evr_machine =3D { > + =C2=A0 =C2=A0.name =3D "lm32-evr", > + =C2=A0 =C2=A0.desc =3D "LatticeMico32 EVR32 eval system", > + =C2=A0 =C2=A0.init =3D lm32_evr_init, > + =C2=A0 =C2=A0.is_default =3D 1 > +}; > + > +static QEMUMachine lm32_uclinux_machine =3D { > + =C2=A0 =C2=A0.name =3D "lm32-uclinux", > + =C2=A0 =C2=A0.desc =3D "lm32 platform for uClinux and u-boot by Theobro= ma Systems", > + =C2=A0 =C2=A0.init =3D lm32_uclinux_init, > + =C2=A0 =C2=A0.is_default =3D 0 > +}; > + > +static void lm32_machine_init(void) > +{ > + =C2=A0 =C2=A0qemu_register_machine(&lm32_uclinux_machine); > + =C2=A0 =C2=A0qemu_register_machine(&lm32_evr_machine); > +} > + > +machine_init(lm32_machine_init); > -- > 1.7.2.3 > > >