From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=33108 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OtiGU-0001vB-89 for qemu-devel@nongnu.org; Thu, 09 Sep 2010 10:38:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OtiGQ-0002K8-SU for qemu-devel@nongnu.org; Thu, 09 Sep 2010 10:38:14 -0400 Received: from mail-qw0-f45.google.com ([209.85.216.45]:47005) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OtiGQ-0002K3-OF for qemu-devel@nongnu.org; Thu, 09 Sep 2010 10:38:10 -0400 Received: by qwh5 with SMTP id 5so472983qwh.4 for ; Thu, 09 Sep 2010 07:38:10 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <1283978392-6313-9-git-send-email-hpoussin@reactos.org> References: <1283978392-6313-1-git-send-email-hpoussin@reactos.org> <1283978392-6313-9-git-send-email-hpoussin@reactos.org> From: Blue Swirl Date: Thu, 9 Sep 2010 14:37:50 +0000 Message-ID: Subject: Re: [Qemu-devel] [PATCH 8/8] [MIPS] qdev: convert rc4030 to sysbus device Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?UTF-8?Q?Herv=C3=A9_Poussineau?= Cc: qemu-devel@nongnu.org 2010/9/8 Herv=C3=A9 Poussineau : > Use it in Jazz emulation > Remove rc4030_init() function, which is not used anymore > > Signed-off-by: Herv=C3=A9 Poussineau > --- > =C2=A0hw/mips.h =C2=A0 =C2=A0 =C2=A0| =C2=A0 =C2=A04 +- > =C2=A0hw/mips_jazz.c | =C2=A0 =C2=A08 +-- > =C2=A0hw/rc4030.c =C2=A0 =C2=A0| =C2=A0135 ++++++++++++++++++++++++++----= ------------------------- > =C2=A03 files changed, 69 insertions(+), 78 deletions(-) > > diff --git a/hw/mips.h b/hw/mips.h > index 2897ea6..bdbe024 100644 > --- a/hw/mips.h > +++ b/hw/mips.h > @@ -16,8 +16,8 @@ typedef struct rc4030DMAState *rc4030_dma; > =C2=A0void rc4030_dma_memory_rw(void *opaque, target_phys_addr_t addr, ui= nt8_t *buf, int len, int is_write); > =C2=A0void rc4030_dma_read(void *dma, uint8_t *buf, int len); > =C2=A0void rc4030_dma_write(void *dma, uint8_t *buf, int len); > - > -void *rc4030_init(qemu_irq timer, rc4030_dma **dmas); > +extern rc4030_dma *rc4030_dmas; > +extern void *rc4030_dma_opaque; These should be device properties (DEFINE_PROP_PTR, qdev_set_prop_ptr(). > > =C2=A0/* dp8393x.c */ > =C2=A0void dp83932_init(NICInfo *nd, target_phys_addr_t base, int it_shif= t, > diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c > index 56739db..eec30c8 100644 > --- a/hw/mips_jazz.c > +++ b/hw/mips_jazz.c > @@ -133,8 +133,6 @@ void mips_jazz_init (ram_addr_t ram_size, > =C2=A0 =C2=A0 CPUState *env; > =C2=A0 =C2=A0 DeviceState *dev; > =C2=A0 =C2=A0 qemu_irq rc4030[16], *i8259; > - =C2=A0 =C2=A0rc4030_dma *dmas; > - =C2=A0 =C2=A0void* rc4030_opaque; > =C2=A0 =C2=A0 int s_rtc, s_dma_dummy; > =C2=A0 =C2=A0 NICInfo *nd; > =C2=A0 =C2=A0 PITState *pit; > @@ -196,7 +194,7 @@ void mips_jazz_init (ram_addr_t ram_size, > =C2=A0 =C2=A0 =C2=A0 =C2=A0 rc4030[n] =3D qdev_get_gpio_in(dev, n); > =C2=A0 =C2=A0 } > > - =C2=A0 =C2=A0rc4030_opaque =3D rc4030_init(env->irq[6], &dmas); > + =C2=A0 =C2=A0sysbus_create_simple("rc4030", 0x80000000, env->irq[6]); > =C2=A0 =C2=A0 s_dma_dummy =3D cpu_register_io_memory(dma_dummy_read, dma_= dummy_write, NULL); > =C2=A0 =C2=A0 cpu_register_physical_memory(0x8000d000, 0x00001000, s_dma_= dummy); > > @@ -237,7 +235,7 @@ void mips_jazz_init (ram_addr_t ram_size, > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 nd->model =3D qemu_strdup("dp83= 932"); > =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (strcmp(nd->model, "dp83932") =3D=3D 0) { > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 dp83932_init(nd, 0x80001000, 2,= rc4030[4], > - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 rc4030_opaque, rc4030_dma_memory_rw); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 rc4030_dma_opaque, rc4030_dma_memory_rw); > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > =C2=A0 =C2=A0 =C2=A0 =C2=A0 } else if (strcmp(nd->model, "?") =3D=3D 0) { > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 fprintf(stderr, "qemu: Supporte= d NICs: dp83932\n"); > @@ -250,7 +248,7 @@ void mips_jazz_init (ram_addr_t ram_size, > > =C2=A0 =C2=A0 /* SCSI adapter */ > =C2=A0 =C2=A0 esp_init(0x80002000, 0, > - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 rc4030_dma_read, rc4030_dma_w= rite, dmas[0], > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 rc4030_dma_read, rc4030_dma_w= rite, rc4030_dmas[0], > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0rc4030[5], &esp_reset); > > =C2=A0 =C2=A0 /* Floppy */ > diff --git a/hw/rc4030.c b/hw/rc4030.c > index 811d12d..0c77c44 100644 > --- a/hw/rc4030.c > +++ b/hw/rc4030.c > @@ -45,6 +45,9 @@ static const char* irq_names[] =3D { "parallel", "flopp= y", "sound", "video", > =C2=A0#define RC4030_ERROR(fmt, ...) \ > =C2=A0do { fprintf(stderr, "rc4030 ERROR: %s: " fmt, __func__ , ## __VA_A= RGS__); } while (0) > > +rc4030_dma *rc4030_dmas =3D NULL; > +void *rc4030_dma_opaque =3D NULL; > + > =C2=A0/********************************************************/ > =C2=A0/* rc4030 emulation =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 */ > > @@ -584,9 +587,8 @@ static void jazzio_reset(JazzIoState* s) > =C2=A0 =C2=A0 qemu_irq_lower(s->irq); > =C2=A0} > > -static void rc4030_reset(void *opaque) > +static void rc4030_reset(rc4030State *s) > =C2=A0{ > - =C2=A0 =C2=A0rc4030State *s =3D opaque; > =C2=A0 =C2=A0 int i; > > =C2=A0 =C2=A0 s->config =3D 0x410; /* some boards seem to accept 0x104 to= o */ > @@ -611,63 +613,6 @@ static void rc4030_reset(void *opaque) > =C2=A0 =C2=A0 qemu_irq_lower(s->timer_irq); > =C2=A0} > > -static int rc4030_load(QEMUFile *f, void *opaque, int version_id) > -{ > - =C2=A0 =C2=A0rc4030State* s =3D opaque; > - =C2=A0 =C2=A0int i, j; > - > - =C2=A0 =C2=A0if (version_id !=3D 2) > - =C2=A0 =C2=A0 =C2=A0 =C2=A0return -EINVAL; > - > - =C2=A0 =C2=A0s->config =3D qemu_get_be32(f); > - =C2=A0 =C2=A0s->invalid_address_register =3D qemu_get_be32(f); > - =C2=A0 =C2=A0for (i =3D 0; i < 8; i++) > - =C2=A0 =C2=A0 =C2=A0 =C2=A0for (j =3D 0; j < 4; j++) > - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0s->dma_regs[i][j] =3D qemu_get= _be32(f); > - =C2=A0 =C2=A0s->dma_tl_base =3D qemu_get_be32(f); > - =C2=A0 =C2=A0s->dma_tl_limit =3D qemu_get_be32(f); > - =C2=A0 =C2=A0s->cache_maint =3D qemu_get_be32(f); > - =C2=A0 =C2=A0s->remote_failed_address =3D qemu_get_be32(f); > - =C2=A0 =C2=A0s->memory_failed_address =3D qemu_get_be32(f); > - =C2=A0 =C2=A0s->cache_ptag =3D qemu_get_be32(f); > - =C2=A0 =C2=A0s->cache_ltag =3D qemu_get_be32(f); > - =C2=A0 =C2=A0s->cache_bmask =3D qemu_get_be32(f); > - =C2=A0 =C2=A0s->offset210 =3D qemu_get_be32(f); > - =C2=A0 =C2=A0s->nvram_protect =3D qemu_get_be32(f); > - =C2=A0 =C2=A0for (i =3D 0; i < 15; i++) > - =C2=A0 =C2=A0 =C2=A0 =C2=A0s->rem_speed[i] =3D qemu_get_be32(f); > - =C2=A0 =C2=A0s->itr =3D qemu_get_be32(f); > - > - =C2=A0 =C2=A0set_next_tick(s); > - > - =C2=A0 =C2=A0return 0; > -} > - > -static void rc4030_save(QEMUFile *f, void *opaque) > -{ > - =C2=A0 =C2=A0rc4030State* s =3D opaque; > - =C2=A0 =C2=A0int i, j; > - > - =C2=A0 =C2=A0qemu_put_be32(f, s->config); > - =C2=A0 =C2=A0qemu_put_be32(f, s->invalid_address_register); > - =C2=A0 =C2=A0for (i =3D 0; i < 8; i++) > - =C2=A0 =C2=A0 =C2=A0 =C2=A0for (j =3D 0; j < 4; j++) > - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0qemu_put_be32(f, s->dma_regs[i= ][j]); > - =C2=A0 =C2=A0qemu_put_be32(f, s->dma_tl_base); > - =C2=A0 =C2=A0qemu_put_be32(f, s->dma_tl_limit); > - =C2=A0 =C2=A0qemu_put_be32(f, s->cache_maint); > - =C2=A0 =C2=A0qemu_put_be32(f, s->remote_failed_address); > - =C2=A0 =C2=A0qemu_put_be32(f, s->memory_failed_address); > - =C2=A0 =C2=A0qemu_put_be32(f, s->cache_ptag); > - =C2=A0 =C2=A0qemu_put_be32(f, s->cache_ltag); > - =C2=A0 =C2=A0qemu_put_be32(f, s->cache_bmask); > - =C2=A0 =C2=A0qemu_put_be32(f, s->offset210); > - =C2=A0 =C2=A0qemu_put_be32(f, s->nvram_protect); > - =C2=A0 =C2=A0for (i =3D 0; i < 15; i++) > - =C2=A0 =C2=A0 =C2=A0 =C2=A0qemu_put_be32(f, s->rem_speed[i]); > - =C2=A0 =C2=A0qemu_put_be32(f, s->itr); > -} > - > =C2=A0void rc4030_dma_memory_rw(void *opaque, target_phys_addr_t addr, ui= nt8_t *buf, int len, int is_write) > =C2=A0{ > =C2=A0 =C2=A0 rc4030State *s =3D opaque; > @@ -788,28 +733,75 @@ static rc4030_dma *rc4030_allocate_dmas(void *opaqu= e, int n) > =C2=A0 =C2=A0 return s; > =C2=A0} > > -void *rc4030_init(qemu_irq timer, rc4030_dma **dmas) > +static int rc4030_post_load(void *opaque, int version_id) > =C2=A0{ > - =C2=A0 =C2=A0rc4030State *s; > - =C2=A0 =C2=A0int s_chipset; > - > - =C2=A0 =C2=A0s =3D qemu_mallocz(sizeof(rc4030State)); > + =C2=A0 =C2=A0rc4030State *s =3D opaque; > + =C2=A0 =C2=A0set_next_tick(s); > + =C2=A0 =C2=A0return 0; > +} > > - =C2=A0 =C2=A0*dmas =3D rc4030_allocate_dmas(s, 4); > +static const VMStateDescription vmstate_rc4030 =3D { > + =C2=A0 =C2=A0.name =3D "rc4030", > + =C2=A0 =C2=A0.version_id =3D 0, > + =C2=A0 =C2=A0.minimum_version_id =3D 0, > + =C2=A0 =C2=A0.minimum_version_id_old =3D 0, > + =C2=A0 =C2=A0.post_load =3D rc4030_post_load, > + =C2=A0 =C2=A0.fields =3D (VMStateField []) { > + =C2=A0 =C2=A0 =C2=A0 =C2=A0VMSTATE_UINT32(config, rc4030State), > + =C2=A0 =C2=A0 =C2=A0 =C2=A0VMSTATE_UINT32(invalid_address_register, rc4= 030State), > + =C2=A0 =C2=A0 =C2=A0 =C2=A0VMSTATE_BUFFER_UNSAFE(dma_regs, rc4030State,= 0, 8 * 3 * sizeof(uint32_t)), > + =C2=A0 =C2=A0 =C2=A0 =C2=A0VMSTATE_UINT32(dma_tl_base, rc4030State), > + =C2=A0 =C2=A0 =C2=A0 =C2=A0VMSTATE_UINT32(dma_tl_limit, rc4030State), > + =C2=A0 =C2=A0 =C2=A0 =C2=A0VMSTATE_UINT32(cache_maint, rc4030State), > + =C2=A0 =C2=A0 =C2=A0 =C2=A0VMSTATE_UINT32(remote_failed_address, rc4030= State), > + =C2=A0 =C2=A0 =C2=A0 =C2=A0VMSTATE_UINT32(memory_failed_address, rc4030= State), > + =C2=A0 =C2=A0 =C2=A0 =C2=A0VMSTATE_UINT32(cache_ptag, rc4030State), > + =C2=A0 =C2=A0 =C2=A0 =C2=A0VMSTATE_UINT32(cache_ltag, rc4030State), > + =C2=A0 =C2=A0 =C2=A0 =C2=A0VMSTATE_UINT32(cache_bmask, rc4030State), > + =C2=A0 =C2=A0 =C2=A0 =C2=A0VMSTATE_UINT32(offset210, rc4030State), > + =C2=A0 =C2=A0 =C2=A0 =C2=A0VMSTATE_UINT32(nvram_protect, rc4030State), > + =C2=A0 =C2=A0 =C2=A0 =C2=A0VMSTATE_UINT32_ARRAY(rem_speed, rc4030State,= 16), > + =C2=A0 =C2=A0 =C2=A0 =C2=A0VMSTATE_UINT32(itr, rc4030State), > + =C2=A0 =C2=A0 =C2=A0 =C2=A0VMSTATE_END_OF_LIST() > + =C2=A0 =C2=A0} > +}; > > - =C2=A0 =C2=A0s->periodic_timer =3D qemu_new_timer(vm_clock, rc4030_peri= odic_timer, s); > - =C2=A0 =C2=A0s->timer_irq =3D timer; > +typedef struct { > + =C2=A0 =C2=A0SysBusDevice busdev; > + =C2=A0 =C2=A0rc4030State rc4030; > +} SysBusRc4030State; > > - =C2=A0 =C2=A0qemu_register_reset(rc4030_reset, s); > - =C2=A0 =C2=A0register_savevm(NULL, "rc4030", 0, 2, rc4030_save, rc4030_= load, s); > +static void rc4030_sysbus_reset(DeviceState *d) > +{ > + =C2=A0 =C2=A0rc4030State *s =3D &container_of(d, SysBusRc4030State, bus= dev.qdev)->rc4030; > =C2=A0 =C2=A0 rc4030_reset(s); > +} > + > +static int rc4030_sysbus_initfn(SysBusDevice *dev) > +{ > + =C2=A0 =C2=A0rc4030State *s =3D &FROM_SYSBUS(SysBusRc4030State, dev)->r= c4030; > + =C2=A0 =C2=A0int s_chipset; > + > + =C2=A0 =C2=A0rc4030_dmas =3D rc4030_allocate_dmas(s, 4); > + =C2=A0 =C2=A0rc4030_dma_opaque =3D s; > + > + =C2=A0 =C2=A0s->periodic_timer =3D qemu_new_timer(vm_clock, rc4030_peri= odic_timer, s); > + =C2=A0 =C2=A0sysbus_init_irq(dev, &s->timer_irq); > > =C2=A0 =C2=A0 s_chipset =3D cpu_register_io_memory(rc4030_read, rc4030_wr= ite, s); > - =C2=A0 =C2=A0cpu_register_physical_memory(0x80000000, 0x300, s_chipset)= ; > + =C2=A0 =C2=A0sysbus_init_mmio(dev, 0x300, s_chipset); > > - =C2=A0 =C2=A0return s; > + =C2=A0 =C2=A0return 0; > =C2=A0} > > +static SysBusDeviceInfo rc4030_sysbus_info =3D { > + =C2=A0 =C2=A0.qdev.name =C2=A0=3D "rc4030", > + =C2=A0 =C2=A0.qdev.size =C2=A0=3D sizeof(SysBusRc4030State), > + =C2=A0 =C2=A0.qdev.vmsd =C2=A0=3D &vmstate_rc4030, > + =C2=A0 =C2=A0.qdev.reset =3D rc4030_sysbus_reset, > + =C2=A0 =C2=A0.init =C2=A0 =C2=A0 =C2=A0 =3D rc4030_sysbus_initfn, > +}; > + > =C2=A0static int jazzio_post_load(void *opaque, int version_id) > =C2=A0{ > =C2=A0 =C2=A0 JazzIoState *s =3D opaque; > @@ -878,6 +870,7 @@ static SysBusDeviceInfo jazzio_sysbus_info =3D { > > =C2=A0static void jazz_register(void) > =C2=A0{ > + =C2=A0 =C2=A0sysbus_register_withprop(&rc4030_sysbus_info); > =C2=A0 =C2=A0 sysbus_register_withprop(&jazzio_sysbus_info); > =C2=A0} > > -- > 1.7.1.GIT > > >