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From: Blue Swirl <blauwirbel@gmail.com>
Date: Sat, 27 Nov 2010 10:05:09 +0000
Message-ID: <AANLkTik6G2ja=d-nG3wixsvza-Jfm6cB5NQwWbT-_RLu@mail.gmail.com>
Subject: Re: [Qemu-devel] [PATCH 01/15] exec: introduce endianness swapped mmio
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To: Paul Brook <paul@codesourcery.com>
Cc: =?UTF-8?Q?Andreas_F=C3=A4rber?= <andreas.faerber@web.de>, Alexander Graf <agraf@suse.de>, QEMU-devel Developers <qemu-devel@nongnu.org>

On Fri, Nov 26, 2010 at 11:47 PM, Paul Brook <paul@codesourcery.com> wrote:
>> > diff --git a/exec.c b/exec.c
>> > index db9ff55..f54a360 100644
>> > --- a/exec.c
>> > +++ b/exec.c
>> >
>> > @@ -3370,6 +3474,22 @@ static int cpu_register_io_memory_fixed(int
>> > io_index,
>> >
>> > =C2=A0 =C2=A0 }
>> > =C2=A0 =C2=A0 io_mem_opaque[io_index] =3D opaque;
>> >
>> > + =C2=A0 =C2=A0switch (endian) {
>> > + =C2=A0 =C2=A0case DEVICE_BIG_ENDIAN:
>> > +#ifndef TARGET_WORDS_BIGENDIAN
>> > + =C2=A0 =C2=A0 =C2=A0 =C2=A0swapendian_init(io_index);
>> > +#endif
>> > + =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
>>
>> So basically, you just moved the #ifdefs to another place. :)
>
> Many #ifdefs inconsistently scattered through all the device code have be=
en
> replaced by a single #ifdef.
>
>> Shouldn't this be dependent on the CPU state and determined at
>> runtime? Thinking of MSR LE bit on ppc. I guess QEMU doesn't support
>> bi-endian ppc today, as does the 970, but it would be nice to keep it
>> in mind.
>
> Switching endianness of a CPU generally does not effect the endianness of=
 the
> CPU/peripheral busses. =C2=A0It makes the CPU byteswap accesses before th=
ey are
> seen by either memory or devices.
>
> In theory it might be possible to avoid redundant byteswaps if you're rea=
lly
> clever. =C2=A0In practice you still have to handle the fact that your dev=
ices are a
> different endianness to RAM, so it probably doesn't gain you a whole lot.

Sparc64 MMU can also perform byte swapping, there is also a byte
swapping CPU mode and byte swapping access instructions. I think only
the instructions are used (for PCI).