From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=54931 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Pc4m1-00045w-0f for qemu-devel@nongnu.org; Sun, 09 Jan 2011 18:34:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Pc4lk-0005Zr-7e for qemu-devel@nongnu.org; Sun, 09 Jan 2011 18:33:53 -0500 Received: from mail-fx0-f45.google.com ([209.85.161.45]:60126) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Pc4lk-0005Zm-1p for qemu-devel@nongnu.org; Sun, 09 Jan 2011 18:33:52 -0500 Received: by fxm12 with SMTP id 12so18062893fxm.4 for ; Sun, 09 Jan 2011 15:33:50 -0800 (PST) MIME-Version: 1.0 In-Reply-To: <20110109224002.GC21189@volta.aurel32.net> References: <1294350874-6885-1-git-send-email-aurelien@aurel32.net> <1294350874-6885-3-git-send-email-aurelien@aurel32.net> <20110107144035.GA18176@hall.aurel32.net> <20110109224002.GC21189@volta.aurel32.net> Date: Mon, 10 Jan 2011 00:33:50 +0100 Message-ID: Subject: Re: [Qemu-devel] [PATCH 3/3] tcg/arm: improve constant loading From: andrzej zaborowski Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Aurelien Jarno Cc: qemu-devel@nongnu.org On 9 January 2011 23:40, Aurelien Jarno wrote: > On Fri, Jan 07, 2011 at 04:56:32PM +0100, andrzej zaborowski wrote: >> On 7 January 2011 15:40, Aurelien Jarno wrote: >> > On Fri, Jan 07, 2011 at 01:52:25PM +0100, andrzej zaborowski wrote: >> >> On 6 January 2011 22:54, Aurelien Jarno wrote: >> >> ... >> >> > =C2=A0 =C2=A0 =C2=A0 =C2=A0 } >> >> > + =C2=A0 =C2=A0} else { >> >> > + =C2=A0 =C2=A0 =C2=A0 =C2=A0int opc =3D ARITH_MOV; >> >> > + =C2=A0 =C2=A0 =C2=A0 =C2=A0int rn =3D 0; >> >> > + >> >> > + =C2=A0 =C2=A0 =C2=A0 =C2=A0do { >> >> > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0int i, rot; >> >> > + >> >> > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0i =3D ctz32(arg) & ~1; >> >> > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0rot =3D ((32 - i) << 7) = & 0xf00; >> >> > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0tcg_out_dat_imm(s, cond,= opc, rd, rn, ((arg >> i) & 0xff) | rot); >> >> > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0arg &=3D ~(0xff << i); >> >> > + >> >> > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0opc =3D ARITH_ORR; >> >> > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0rn =3D rd; >> >> >> >> I think you could get rid of rn and just use rd from the start of the >> >> loop. =C2=A0Otherwise acked by me too. >> >> >> > >> > What do you mean exactly? rn has to be 0 when opc is ARITH_MOV in orde= r >> > to generate a correct ARM instruction. >> >> According to my ARM926 manual rn is ignored for MOV/MVN, perhaps it's >> different in later revisions. >> > > I have just tried, and it actually works (tried on ARMv5 and ARMv7). Also works under qemu-arm :) > Note that binutils is not able to disassemble such an instruction and > outputs in qemu.log something like: > | 0x01000008: =C2=A0e3aa50ff =C2=A0undefined instruction 0xe3aa50ff > > However what worries me the most is that the "ARM Architecture Reference > Manual ARMv7-A and ARMv7-R edition" defines this opcode with the rn field > as "(0)(0)(0)(0)". Looking at what it means: > > | An instruction is UNPREDICTABLE if: > | [...] > | * the pseudocode for that encoding does not indicate that a different > |=C2=A0 =C2=A0special case applies, and a bit marked (0) or (1) in the en= coding > | diagram of an instruction is not 0 or 1 respectively. > > In short is it still going to work on newer CPUs? Perhaps let's be on the safe side and use your version with rn =3D 0. I think it *should* work on the new ARM ISAs because of backwards compatibility: x works under ARMv4 & ARMv5 and x is not listed under the differences between new and old ISA, thus it needs to work under a new ISA. Cheers