Re: [Qemu-devel] [PATCH 4/4] target-arm: Fix decoding of Thumb preload and hint space

[Peter Maydell <peter.maydell@linaro.org>]

On 3 February 2011 19:43, Peter Maydell <peter.maydell@linaro.org> wrote:
> @@ -8326,9 +8362,8 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
>                 imm = insn & 0xfff;
>                 tcg_gen_addi_i32(addr, addr, imm);
>             } else {
> -                op = (insn >> 8) & 7;
>                 imm = insn & 0xff;
> -                switch (op) {
> +                switch ((insn >> 8) & 7) {
>                 case 0: case 8: /* Shifted Register.  */
>                     shift = (insn >> 4) & 0xf;
>                     if (shift > 3)

It's pretty obvious from the combination of "switch (something & 7)" with
"case 8:" that the load/store address decode logic here is bogus, but
since that's unrelated to the preload/hint space I'm going to address
it in a separate patchset later.

-- PMM