From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=58020 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OFl1U-0004y9-1B for qemu-devel@nongnu.org; Sat, 22 May 2010 05:29:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OFl1R-00029D-Tv for qemu-devel@nongnu.org; Sat, 22 May 2010 05:29:35 -0400 Received: from mail-ww0-f45.google.com ([74.125.82.45]:52442) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OFl1R-000291-Eh for qemu-devel@nongnu.org; Sat, 22 May 2010 05:29:33 -0400 Received: by wwb39 with SMTP id 39so717937wwb.4 for ; Sat, 22 May 2010 02:29:32 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: References: <1274517536-20889-1-git-send-email-atar4qemu@gmail.com> From: Artyom Tarasenko Date: Sat, 22 May 2010 11:29:12 +0200 Message-ID: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] Re: [PATCH] sparc32 protect read-only bits in DMA CSR registers List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Blue Swirl Cc: qemu-devel@nongnu.org 2010/5/22 Blue Swirl : > Thanks, applied. You forgot SoB-line, I copied it from the previous versi= on. Sorry. Btw, is there a way to tell 'format-patch' to always include it? Can't find it in the git docs. Otherwise I'll define an alias so I won't need to remember about the '-s' switch. > On Sat, May 22, 2010 at 8:38 AM, Artyom Tarasenko > wrote: >> On a real hardware changing read-only bits has no effect >> Use a mask common for SCSI and Ethernet registers. The crucial >> bit is DMA_INTR, because setting or clearing it may produce >> spurious interrupts. >> >> This patch allows booting Solaris 2.3 >> --- >> =A0hw/sparc32_dma.c | =A0 12 ++++++++---- >> =A01 files changed, 8 insertions(+), 4 deletions(-) >> >> diff --git a/hw/sparc32_dma.c b/hw/sparc32_dma.c >> index 3ceb851..b521707 100644 >> --- a/hw/sparc32_dma.c >> +++ b/hw/sparc32_dma.c >> @@ -62,6 +62,9 @@ >> =A0#define DMA_DRAIN_FIFO 0x40 >> =A0#define DMA_RESET 0x80 >> >> +/* XXX SCSI and ethernet should have different read-only bit masks */ >> +#define DMA_CSR_RO_MASK 0xfe000007 >> + >> =A0typedef struct DMAState DMAState; >> >> =A0struct DMAState { >> @@ -187,7 +190,7 @@ static void dma_mem_writel(void *opaque, target_phys= _addr_t addr, uint32_t val) >> =A0 =A0 switch (saddr) { >> =A0 =A0 case 0: >> =A0 =A0 =A0 =A0 if (val & DMA_INTREN) { >> - =A0 =A0 =A0 =A0 =A0 =A0if (val & DMA_INTR) { >> + =A0 =A0 =A0 =A0 =A0 =A0if (s->dmaregs[0] & DMA_INTR) { >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 DPRINTF("Raise IRQ\n"); >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 qemu_irq_raise(s->irq); >> =A0 =A0 =A0 =A0 =A0 =A0 } >> @@ -204,16 +207,17 @@ static void dma_mem_writel(void *opaque, target_ph= ys_addr_t addr, uint32_t val) >> =A0 =A0 =A0 =A0 =A0 =A0 val &=3D ~DMA_DRAIN_FIFO; >> =A0 =A0 =A0 =A0 } else if (val =3D=3D 0) >> =A0 =A0 =A0 =A0 =A0 =A0 val =3D DMA_DRAIN_FIFO; >> - =A0 =A0 =A0 =A0val &=3D 0x0fffffff; >> + =A0 =A0 =A0 =A0val &=3D ~DMA_CSR_RO_MASK; >> =A0 =A0 =A0 =A0 val |=3D DMA_VER; >> + =A0 =A0 =A0 =A0s->dmaregs[0] =3D (s->dmaregs[0] & DMA_CSR_RO_MASK) | v= al; >> =A0 =A0 =A0 =A0 break; >> =A0 =A0 case 1: >> =A0 =A0 =A0 =A0 s->dmaregs[0] |=3D DMA_LOADED; >> - =A0 =A0 =A0 =A0break; >> + =A0 =A0 =A0 =A0/* fall through */ >> =A0 =A0 default: >> + =A0 =A0 =A0 =A0s->dmaregs[saddr] =3D val; >> =A0 =A0 =A0 =A0 break; >> =A0 =A0 } >> - =A0 =A0s->dmaregs[saddr] =3D val; >> =A0} >> >> =A0static CPUReadMemoryFunc * const dma_mem_read[3] =3D { >> -- >> 1.6.2.5 >> >> > --=20 Regards, Artyom Tarasenko solaris/sparc under qemu blog: http://tyom.blogspot.com/