From: Blue Swirl <blauwirbel@gmail.com>
To: Artyom Tarasenko <atar4qemu@googlemail.com>
Cc: qemu-devel@nongnu.org, Artyom Tarasenko <atar4qemu@gmail.com>
Subject: [Qemu-devel] Re: [PATCH] sparc32 esp fix spurious interrupts in chip reset
Date: Tue, 1 Jun 2010 17:42:17 +0000 [thread overview]
Message-ID: <AANLkTil6HsFU422XJ9LMOHEKyS1iTH2aDU7Shzu2sVF8@mail.gmail.com> (raw)
In-Reply-To: <1275258946-15739-1-git-send-email-atar4qemu@gmail.com>
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On Sun, May 30, 2010 at 10:35 PM, Artyom Tarasenko
<atar4qemu@googlemail.com> wrote:
> lower interrupt during chip reset. Otherwise the ESP_RSTAT register
> may get out of sync with the IRQ line status. This effect became
> visible after commit 65899fe3
Hard reset handlers should not touch qemu_irqs, because on cold start,
the receiving end may be unprepared to handle the signal. See
0d0a7e69e853639b123798877e019c3c7ee6634a,
bc26e55a6615dc594be425d293db40d5cdcdb84b and
42f1ced228c9b616cfa2b69846025271618e4ef5.
For ESP there are two other sources of reset: signal from DMA and chip
reset command. On those cases, lowering IRQ makes sense.
So the correct fix is to refactor the reset handling a bit. Does this
patch also fix your test case?
[-- Attachment #2: 0001-esp-lower-IRQ-on-soft-reset.patch --]
[-- Type: application/x-patch, Size: 2025 bytes --]
next prev parent reply other threads:[~2010-06-01 17:42 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-05-30 22:35 [Qemu-devel] [PATCH] sparc32 esp fix spurious interrupts in chip reset Artyom Tarasenko
2010-06-01 17:42 ` Blue Swirl [this message]
2010-06-01 19:56 ` [Qemu-devel] " Artyom Tarasenko
2010-06-01 20:09 ` Blue Swirl
2010-06-01 20:16 ` Artyom Tarasenko
2010-06-04 19:13 ` Blue Swirl
2010-06-04 20:30 ` Artyom Tarasenko
2010-06-09 20:35 ` Blue Swirl
2010-06-10 8:15 ` Artyom Tarasenko
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