From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=48453 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OWaPu-0001ql-UQ for qemu-devel@nongnu.org; Wed, 07 Jul 2010 15:36:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OWaPi-00016e-6D for qemu-devel@nongnu.org; Wed, 07 Jul 2010 15:36:11 -0400 Received: from mail-px0-f173.google.com ([209.85.212.173]:49596) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OWaPi-00015i-1T for qemu-devel@nongnu.org; Wed, 07 Jul 2010 15:36:10 -0400 Received: by pxi18 with SMTP id 18so1983pxi.4 for ; Wed, 07 Jul 2010 12:36:06 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: References: From: Blue Swirl Date: Wed, 7 Jul 2010 19:29:09 +0000 Message-ID: Subject: Re: [Qemu-devel] [PATCH, RFC] pci: handle BAR mapping at pci level Content-Type: text/plain; charset=UTF-8 List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: malc Cc: qemu-devel , "Michael S. Tsirkin" On Wed, Jul 7, 2010 at 6:15 PM, malc wrote: > On Wed, 7 Jul 2010, Blue Swirl wrote: > >> Add I/O port registration functions which separate registration >> from the mapping stage. > > Why? So that the device code can specify all other parameters except for the I/O port, which will be handled by PCI BAR mappings.